Commit fa2f81b0 authored by Tom Rini's avatar Tom Rini
Browse files

TI: Rework SRAM definitions and maximums



On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area.  As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow.  As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.

Tested on OMAP4 Pandaboard, OMAP3 Beagle xM

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Weber <weber@corscience.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: "B, Ravi" <ravibabu@ti.com>
Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Signed-off-by: default avatarTom Rini <trini@konsulko.com>
Tested-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Acked-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
Tested-by: default avatarLadislav Michl <ladis@linux-mips.org>
parent 31c98cbb
......@@ -15,24 +15,23 @@
#ifndef _OMAP_H_
#define _OMAP_H_
#include <linux/sizes.h>
#ifdef CONFIG_AM33XX
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800
#define NON_SECURE_SRAM_IMG_END 0x4030B800
#elif defined(CONFIG_TI81XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define SRAM_SCRATCH_SPACE_ADDR 0x4031B800
#define NON_SECURE_SRAM_IMG_END 0x4031B800
#elif defined(CONFIG_AM43XX)
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40340000
#define SRAM_SCRATCH_SPACE_ADDR 0x40337C00
#define AM4372_BOARD_NAME_START SRAM_SCRATCH_SPACE_ADDR
#define AM4372_BOARD_NAME_END SRAM_SCRATCH_SPACE_ADDR + 0xC
#define AM4372_BOARD_VERSION_START SRAM_SCRATCH_SPACE_ADDR + 0xD
#define AM4372_BOARD_VERSION_END SRAM_SCRATCH_SPACE_ADDR + 0x14
#define NON_SECURE_SRAM_IMG_END 0x40337DE0
#define QSPI_BASE 0x47900000
#endif
#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* Boot parameters */
#ifndef __ASSEMBLY__
......
......@@ -10,6 +10,8 @@
#ifndef _OMAP3_H_
#define _OMAP3_H_
#include <linux/sizes.h>
/* Stuff on L3 Interconnect */
#define SMX_APE_BASE 0x68000000
......@@ -145,7 +147,8 @@ struct gpio {
#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
#define NON_SECURE_SRAM_END 0x40210000
#define SRAM_SCRATCH_SPACE_ADDR 0x4020E000
#define NON_SECURE_SRAM_IMG_END 0x4020F000
#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
......
......@@ -19,6 +19,8 @@
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#include <linux/sizes.h>
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
......@@ -109,7 +111,8 @@ struct s32ktimer {
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
#define NON_SECURE_SRAM_IMG_END 0x4030C000
#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
......
......@@ -16,6 +16,8 @@
#include <asm/types.h>
#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
#include <linux/sizes.h>
/*
* L4 Peripherals - L4 Wakeup and L4 Core now
*/
......@@ -186,11 +188,13 @@ struct s32ktimer {
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
#define NON_SECURE_SRAM_IMG_END 0x4037E000
#else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
#define NON_SECURE_SRAM_IMG_END 0x4031E000
#endif
#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
......
......@@ -277,7 +277,8 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -335,7 +335,8 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -37,9 +37,6 @@
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE CONFIG_ISW_ENTRY_ADDR
#define CONFIG_SPL_MAX_SIZE (NON_SECURE_SRAM_END - \
CONFIG_PUB_ROM_DATA_SIZE - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
#define CONFIG_SPL_POWER_SUPPORT
......
......@@ -102,8 +102,6 @@
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_MAX_SIZE (256 << 10) /* 256 KiB */
#endif
/* SPI SPL */
......
......@@ -46,10 +46,12 @@
* area between 0x402F0400 and 0x4030B800 as a download area and
* 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
* supports X-MODEM loading via UART, and we leverage this and then use
* Y-MODEM to load u-boot.img, when booted over UART.
* Y-MODEM to load u-boot.img, when booted over UART. We must also include
* the scratch space that U-Boot uses in SRAM.
*/
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
/*
* Since SPL did pll and ddr initialization for us,
......
......@@ -344,7 +344,8 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
......
......@@ -153,7 +153,6 @@
/* SPL defines. */
#define CONFIG_SPL_TEXT_BASE 0x40300350
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024)
......
......@@ -185,8 +185,6 @@
/* In SPL, use the environment and discard MMC support for space. */
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_SPL_MMC_SUPPORT
#undef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_MAX_SIZE (64 << 10) /* 64 KiB */
#endif
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_ENV_IS_IN_SPI_FLASH
......
......@@ -119,7 +119,8 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE (48 * 1024)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
......
......@@ -343,7 +343,8 @@
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -16,11 +16,11 @@
#include <configs/ti_omap3_common.h>
#include <asm/mach-types.h>
/* SRAM starts at 0x40200000 and ends at 0x4020FFFF (64KB) */
#undef CONFIG_SPL_MAX_SIZE
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_TEXT_BASE 0x40200000
/*
......
......@@ -30,11 +30,13 @@
#include <configs/ti_omap3_common.h>
/* Override default SPL info to minimize empty space and allow BCH8 in SPL */
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
* order to allow for BCH8 to fit in.
*/
#undef CONFIG_SPL_TEXT_BASE
#undef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_TEXT_BASE 0x40200000
/* Display CPU and Board information */
......
......@@ -11,10 +11,12 @@
#define CONFIG_NAND
#include <configs/ti_omap3_common.h>
#undef CONFIG_SPL_MAX_SIZE
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
#undef CONFIG_SPL_TEXT_BASE
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_BCH
......
......@@ -124,7 +124,8 @@
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -126,7 +126,8 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200000
#define CONFIG_SPL_MAX_SIZE (54 * 1024)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
......
......@@ -218,7 +218,8 @@
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
......
......@@ -326,7 +326,8 @@
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
......
......@@ -157,7 +157,8 @@
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -123,7 +123,8 @@
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40400000
#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024)
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
......
......@@ -58,7 +58,6 @@
* Y-MODEM to load u-boot.img, when booted over UART.
*/
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
(128 << 20))
......
......@@ -212,14 +212,14 @@
/*
* Place the image at the start of the ROM defined image space (per
* CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
* downloaded image area. We initalize DRAM as soon as we can so that
* we can place stack, malloc and BSS there. We load U-Boot itself into
* memory at 0x80800000 for legacy reasons (to not conflict with older
* SPLs). We have our BSS be placed 2MiB after this, to allow for the
* default Linux kernel address of 0x80008000 to work with most sized
* kernels, in the Falcon Mode case. We have the SPL malloc pool at the
* end of the BSS area. We suggest that the stack be placed at 32MiB after
* the start of DRAM to allow room for all of the above (handled in Kconfig).
* downloaded image area minus 1KiB for scratch space. We initalize DRAM as
* soon as we can so that we can place stack, malloc and BSS there. We load
* U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict
* with older SPLs). We have our BSS be placed 2MiB after this, to allow for
* the default Linux kernel address of 0x80008000 to work with most sized
* kernels, in the Falcon Mode case. We have the SPL malloc pool at the end
* of the BSS area. We suggest that the stack be placed at 32MiB after the
* start of DRAM to allow room for all of the above (handled in Kconfig).
*/
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
......@@ -233,6 +233,11 @@
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
#endif
#ifndef CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#endif
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
......
......@@ -68,7 +68,6 @@
/* SPL */
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (54 * 1024)
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
......
......@@ -151,7 +151,6 @@
* So moving TEXT_BASE down to non-HS limit.
*/
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
......
......@@ -154,13 +154,6 @@
#define CONFIG_SPL_TEXT_BASE 0x40300000
#endif
/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define TI_ROM_BOOT_LOAD_END 0x4037E000
#else
#define TI_ROM_BOOT_LOAD_END 0x4031E000
#endif
#define CONFIG_SPL_MAX_SIZE (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_DISPLAY_PRINT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
......
......@@ -338,7 +338,8 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
......
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