Commit fb04b621 authored by Luo Ji's avatar Luo Ji

MA-12219 [Android] Fix build errors for imx8mm

Android build use different tool chain(gcc 4.9) with yocto(gcc 6.2),
'for' loop initial declarations are not supported in C90, define the
variable first before use it.

Test: build pass for imx8mm_evk.

Change-Id: Idf9a9f21626a02e2e679d2e74410378cd143c3f1
Signed-off-by: default avatarLuo Ji <ji.luo@nxp.com>
parent 46d9d34a
......@@ -105,10 +105,12 @@ void ddr_load_train_firmware(enum fw_type type)
void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, unsigned int num)
{
int i = 0;
/* enable the ddrphy apb */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
dwc_ddrphy_apb_wr(0xc0080, 0x3);
for (int i = 0; i < num; i++) {
for (i = 0; i < num; i++) {
ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
ddrphy_csr++;
}
......@@ -120,6 +122,7 @@ void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, unsigned int num
void dram_config_save(struct dram_timing_info *timing_info,
unsigned long saved_timing_base)
{
int i = 0;
struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
struct dram_cfg_param *cfg;
......@@ -132,7 +135,7 @@ void dram_config_save(struct dram_timing_info *timing_info,
/* save ddrc config */
saved_timing->ddrc_cfg = cfg;
for (int i = 0; i < timing_info->ddrc_cfg_num; i++) {
for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
cfg->reg = timing_info->ddrc_cfg[i].reg;
cfg->val = timing_info->ddrc_cfg[i].val;
cfg++;
......@@ -140,7 +143,7 @@ void dram_config_save(struct dram_timing_info *timing_info,
/* save ddrphy config */
saved_timing->ddrphy_cfg = cfg;
for (int i = 0; i < timing_info->ddrphy_cfg_num; i++) {
for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
cfg->reg = timing_info->ddrphy_cfg[i].reg;
cfg->val = timing_info->ddrphy_cfg[i].val;
cfg++;
......@@ -148,7 +151,7 @@ void dram_config_save(struct dram_timing_info *timing_info,
/* save the ddrphy csr */
saved_timing->ddrphy_trained_csr = cfg;
for (int i = 0; i < timing_info->ddrphy_trained_csr_num; i++) {
for (i = 0; i < timing_info->ddrphy_trained_csr_num; i++) {
cfg->reg = timing_info->ddrphy_trained_csr[i].reg;
cfg->val = timing_info->ddrphy_trained_csr[i].val;
cfg++;
......@@ -156,7 +159,7 @@ void dram_config_save(struct dram_timing_info *timing_info,
/* save the ddrphy pie */
saved_timing->ddrphy_pie = cfg;
for (int i = 0; i < timing_info->ddrphy_pie_num; i++) {
for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
cfg->reg = timing_info->ddrphy_pie[i].reg;
cfg->val = timing_info->ddrphy_pie[i].val;
cfg++;
......
......@@ -13,11 +13,13 @@ void lpddr4_cfg_phy(struct dram_timing_info *dram_timing)
struct dram_cfg_param *dram_cfg;
struct dram_fsp_msg *fsp_msg;
unsigned int num;
int i = 0;
int j = 0;
/* initialize PHY configuration */
dram_cfg = dram_timing->ddrphy_cfg;
num = dram_timing->ddrphy_cfg_num;
for (int i = 0; i < num; i++) {
for (i = 0; i < num; i++) {
/* config phy reg */
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
......@@ -25,7 +27,7 @@ void lpddr4_cfg_phy(struct dram_timing_info *dram_timing)
/* load the frequency setpoint message block config */
fsp_msg = dram_timing->fsp_msg;
for (int i = 0; i < dram_timing->fsp_msg_num; i++) {
for (i = 0; i < dram_timing->fsp_msg_num; i++) {
printf("DRAM PHY training for %dMTS\n", fsp_msg->drate);
/* set dram PHY input clocks to desired frequency */
ddrphy_init_set_dfi_clk(fsp_msg->drate);
......@@ -37,7 +39,7 @@ void lpddr4_cfg_phy(struct dram_timing_info *dram_timing)
/* load the frequency set point message block parameter */
dram_cfg = fsp_msg->fsp_cfg;
num = fsp_msg->fsp_cfg_num;
for (int j = 0; j < num; j++) {
for (j = 0; j < num; j++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
......@@ -74,7 +76,7 @@ void lpddr4_cfg_phy(struct dram_timing_info *dram_timing)
/* Load PHY Init Engine Image */
dram_cfg = dram_timing->ddrphy_pie;
num = dram_timing->ddrphy_pie_num;
for (int i = 0; i < num; i++) {
for (i = 0; i < num; i++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
......
......@@ -15,7 +15,9 @@
void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
{
for (int i = 0; i < num; i++) {
int i = 0;
for (i = 0; i < num; i++) {
reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
ddrc_cfg++;
}
......
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