* Patch by Leif Lindholm, 23 Sep 2004:

  add support for the AMD db1550 board

* Patch by Travis Sawyer, 15 Sep 2004:
  Add CONFIG_SERIAL_MULTI support for ppc4xx,
  update README.serial_multi

CHANGELOG

@@ -2,6 +2,13 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Leif Lindholm, 23 Sep 2004:
+  add support for the AMD db1550 board
+
+* Patch by Travis Sawyer, 15 Sep 2004:
+  Add CONFIG_SERIAL_MULTI support for ppc4xx,
+  update README.serial_multi
+
 * Patches by David Snowdon, 07 Sep 2004:
   - add u-boot.hex target in the top level Makefile
   - add support for the UNSW/NICTA PLEB 2 board (pleb2)

CREDITS

@@ -253,6 +253,10 @@ E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
 W: http://www.leox.org
 
+N: Leif Lindholm
+E: leif.lindholm@i3micro.com
+D: Support for AMD dbau1550 board.
+
 N: Stephan Linz
 E: linz@li-pro.net
 D: Support for Nios Stratix Development Kit (DK-1S10)

MAKEALL

@@ -180,9 +180,9 @@ LIST_mips4kc="incaip"
 
 LIST_mips5kc="purple"
 
-LIST_au1x00="dbau1000 dbau1100 dbau1500"
+LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
 
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
 
 #########################################################################
 ## i386 Systems

Makefile

@@ -1467,6 +1467,16 @@ dbau1500_config		: 	unconfig
 	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00
 
+dbau1550_config		:	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1550 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1550_el_config	:	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1550 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################

board/dbau1x00/dbau1x00.c

@@ -30,7 +30,7 @@ long int initdram(int board_type)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return 64*1024*1024;
+	return MEM_SIZE*1024*1024;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010
@@ -42,8 +42,8 @@ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
 int checkboard (void)
 {
 	u16 status;
-	volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
-	volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
+	volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
+	volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
 	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
 	u32 proc_id;
 
@@ -67,6 +67,11 @@ int checkboard (void)
 		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
 			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
 		break;
+	case 3:
+		puts ("Board: DbAu1550\n");
+		printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
 	default:
 		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
 	}

board/dbau1x00/memsetup.S

@@ -9,7 +9,8 @@
 #define AU1500_SYS_ADDR		0xB1900000
 #define sys_endian		0x0038
 #define CP0_Config0		$16
-#define MEM_1MS			((396000000/1000000) * 1000)
+#define CPU_SCALE		((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CFG_MHZ) * 1000)
 
 	.text
 	.set noreorder
@@ -23,6 +24,19 @@ memsetup:
 	 * Switch S1.1 Off(bit7 reads 1) is Little Endian
 	 * Switch S1.1 On (bit7 reads 0) is Big Endian
 	 */
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
 	li	t0, MEM_STCFG1
 	li	t1, 0x00000080
 	sw	t1, 0(t0)
@@ -34,9 +48,10 @@ memsetup:
 	li	t0, MEM_STADDR1
 	li	t1, 0x10c03f00
 	sw	t1, 0(t0)
+#endif
 
-	li	t0, 0xAE000008
-	lw	t1,0(t0)
+	li	t0, DB1XX0_BCSR_ADDR
+	lw	t1,8(t0)
 	andi	t1,t1,0x80
 	beq	zero,t1,big_endian
 	nop
@@ -98,10 +113,82 @@ big_endian:
 	mtc0	zero, CP0_WIRED
 	nop
 
+#ifdef CONFIG_DBAU1550
+	/* No workaround if running from ram */
+	lui	t0, 0xffc0
+	lui	t3, 0xbfc0
+	and	t1, ra, t0
+	bne	t1, t3, noCacheJump
+	nop
+
+	/*** From AMD YAMON ***/
+	/*
+	 * Step 8) Initialize the caches
+	 */
+	li		t0, (16*1024)
+	li		t1, 32
+	li		t2, 0x80000000
+	addu	t3, t0, t2
+cacheloop:
+	cache	0, 0(t2)
+	cache	1, 0(t2)
+	addu	t2, t1
+	bne		t2, t3, cacheloop
+	nop
+
+	/* Save return address */
+	move		t3, ra
+
+	/* Run from cacheable space now */
+	bal		cachehere
+	nop
+cachehere:
+	li		t1, ~0x20000000 /* convert to KSEG0 */
+	and		t0, ra, t1
+	addi	t0, 5*4			/* 5 insns beyond cachehere */
+	jr		t0
+	nop
+
+	/* Restore return address */
+	move		ra, t3
+
+	/*
+	 * Step 9) Initialize the TLB
+	 */
+	li		t0, 0			# index value
+	li		t1, 0x00000000		# entryhi value
+	li		t2, 32			# 32 entries
+
+tlbloop:
+	/* Probe TLB for matching EntryHi */
+	mtc0	t1, CP0_ENTRYHI
+	tlbp
+	nop
+
+	/* Examine Index[P], 1=no matching entry */
+	mfc0	t3, CP0_INDEX
+	li	t4, 0x80000000
+	and	t3, t4, t3
+	addiu	t1, t1, 1		# increment t1 (asid)
+	beq	zero, t3, tlbloop
+	nop
+
+	/* Initialize the TLB entry */
+	mtc0	t0, CP0_INDEX
+	mtc0	zero, CP0_ENTRYLO0
+	mtc0	zero, CP0_ENTRYLO1
+	mtc0	zero, CP0_PAGEMASK
+	tlbwi
+
+	/* Do it again */
+	addiu	t0, t0, 1
+	bne	t0, t2, tlbloop
+	nop
+
 	/* First setup pll:s to make serial work ok */
 	/* We have a 12 MHz crystal */
 	li	t0, SYS_CPUPLL
-	li	t1, 0x21  /* 396 MHz */
+	li	t1, CPU_SCALE  /* CPU clock */
 	sw	t1, 0(t0)
 	sync
 	nop
@@ -119,19 +206,49 @@ big_endian:
 	sync
 
 	/*  Static memory controller */
+	/* RCE0 - can not change while fetching, do so from icache */
+	move		t2, ra /* Store return address */
+	bal		getAddr
+	nop
 
-	/* RCE0 AMD 29LV640M MirrorBit Flash */
+getAddr:
+	move		t1, ra
+	move		ra, t2 /* Move return addess back */
+
+	cache	0x14,0(t1)
+	cache	0x14,32(t1)
+	/*** /From YAMON ***/
+
+noCacheJump:
+#endif /* CONFIG_DBAU1550 */
+
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD MirrorBit Flash (?) */
 	li	t0, MEM_STCFG0
-	li	t1, 0x00000013
+	li	t1, 0x00000003
 	sw	t1, 0(t0)
 
+	li	t0, MEM_STADDR0
+	li	t1, 0x11803E00
+	sw	t1, 0(t0)
+#else /* CONFIG_DBAU1550 */
 	li	t0, MEM_STTIME0
-	li	t1, 0x040181D7
+	li	t1, 0x00014C0F
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD 29LV640M MirrorBit Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000013
 	sw	t1, 0(t0)
 
 	li	t0, MEM_STADDR0
 	li	t1, 0x11E03F80
 	sw	t1, 0(t0)
+#endif /* CONFIG_DBAU1550 */
 
 	/* RCE1 CPLD Board Logic */
 	li	t0, MEM_STCFG1
@@ -146,7 +263,20 @@ big_endian:
 	li	t1, 0x10c03f00
 	sw	t1, 0(t0)
 
+#ifdef CONFIG_DBAU1550
 	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
 	li	t0, MEM_STCFG2
 	li	t1, 0x00000000
 	sw	t1, 0(t0)
@@ -158,6 +288,7 @@ big_endian:
 	li	t0, MEM_STADDR2
 	li	t1, 0x00000000
 	sw	t1, 0(t0)
+#endif
 
 	/* RCE3 PCMCIA 250ns */
 	li	t0, MEM_STCFG3
@@ -281,6 +412,99 @@ big_endian:
 	bne	t1, zero, 1b
 	nop
 
+#ifdef CONFIG_DBAU1550
+/* SDCS 0,1,2 DDR SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0xe21003f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0xe21043f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0xe21083f0
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9030060a /* Program refresh - disabled */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDCONFIGB
+	li	t1, 0x00028000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	li	t1, 0
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	sw	zero, 0(t0)
+	sync
+
+	/* Issue 2 autoref */
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	/* Enable refresh */
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9830060a /* Program refresh - enabled */
+	sw	t1, 0(t0)
+	sync
+
+#else /* CONFIG_DBAU1550 */
 /* SDCS 0,1 SDRAM */
 	li	t0, MEM_SDMODE0
 	li	t1, 0x005522AA
@@ -339,6 +563,7 @@ big_endian:
 	sw	t1, 0(t0)
 	sync
 
+#endif /* CONFIG_DBAU1550 */
 	/* wait 1mS after setup */
 	li	t1, MEM_1MS
 1:	add	t1, -1

common/serial.c

@@ -38,6 +38,9 @@ struct serial_device *default_serial_console (void)
 #elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
    || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 	return &serial_scc_device;
+#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
+   || defined(CONFIG_405EP)
+	return &serial0_device;
 #else
 #error No default console
 #endif
@@ -71,6 +74,12 @@ void serial_initialize (void)
 	serial_register (&serial_scc_device);
 #endif
 
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
+ || defined(CONFIG_405EP)
+	serial_register(&serial0_device);
+	serial_register(&serial1_device);
+#endif
+
 	serial_assign (default_serial_console ()->name);
 }
 

cpu/mips/au1x00_eth.c

@@ -46,10 +46,15 @@
 #define ETH0_BASE AU1500_ETH0_BASE
 #define MAC0_ENABLE AU1500_MAC0_ENABLE
 #else
+#ifdef CONFIG_AU1550
+#define ETH0_BASE AU1550_ETH0_BASE
+#define MAC0_ENABLE AU1550_MAC0_ENABLE
+#else
 #error "No valid cpu set"
 #endif
 #endif
 #endif
+#endif
 
 #include <common.h>
 #include <malloc.h>

cpu/mips/au1x00_serial.c

@@ -71,8 +71,8 @@ void serial_setbrg (void)
 	volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
 	volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
 
-	/* Set baudrate to 115200 */
-	*uart_clk = 0x36;
+	/* Set baudrate - FIXME for bus speeds != CPU/2 */
+	*uart_clk = ((CFG_HZ/(CONFIG_BAUDRATE * 64)));
 
 	/* Set parity, stop bits and word length to 8N1 */
 	*uart_lcr = UART_LCR_WLEN8;

cpu/ppc4xx/serial.c

@@ -41,13 +41,20 @@
  * LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  */
 /*------------------------------------------------------------------------------- */
-
+/*
+ * Travis Sawyer 15 September 2004
+ *    Added CONFIG_SERIAL_MULTI support
+ */
 #include <common.h>
 #include <commproc.h>
 #include <asm/processor.h>
 #include <watchdog.h>
 #include "vecnum.h"
 
+#ifdef CONFIG_SERIAL_MULTI
+#include <serial.h>
+#endif
+
 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 #include <malloc.h>
 #endif
@@ -147,7 +154,6 @@
 #define asyncXOFFchar                 0x13
 #define asyncXONchar                  0x11
 
-
 /*
  * Minimal serial functions needed to use one of the SMC ports
  * as serial console interface.
@@ -177,7 +183,6 @@ int serial_init (void)
 	return (0);
 }
 
-
 void serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -190,7 +195,6 @@ void serial_setbrg (void)
 	out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
 }
 
-
 void serial_putc (const char c)
 {
 	if (c == '\n')
@@ -208,7 +212,6 @@ void serial_putc (const char c)
 	}
 }
 
-
 void serial_puts (const char *s)
 {
 	while (*s) {
@@ -216,7 +219,6 @@ void serial_puts (const char *s)
 	}
 }
 
-
 int serial_getc ()
 {
 	unsigned char status = 0;
@@ -240,7 +242,6 @@ int serial_getc ()
 	return (0x000000ff & (int) in8 (asyncRxBufferport1));
 }
 
-
 int serial_tstc ()
 {
 	unsigned char status;
@@ -264,7 +265,6 @@ int serial_tstc ()
 
 #endif	/* CONFIG_IOP480 */
 
-
 /*****************************************************************************/
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
 
@@ -350,7 +350,6 @@ int serial_tstc ()
 /*#define asyncTxBufferport1      ACTING_UART0_BASE+0x00 */
 /*#define asyncRxBufferport1      ACTING_UART0_BASE+0x00 */
 
-
 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 /*-----------------------------------------------------------------------------+
   | Fifo
@@ -364,7 +363,6 @@ typedef struct {
 volatile static serial_buffer_t buf_info;
 #endif
 
-
 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
 static void serial_divs (int baudrate, unsigned long *pudiv,
 			 unsigned short *pbdiv )
@@ -411,14 +409,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
 }
 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
 
-
 /*
  * Minimal serial functions needed to use one of the SMC ports
  * as serial console interface.
  */
 
 #if defined(CONFIG_440)
-int serial_init (void)
+#if defined(CONFIG_SERIAL_MULTI)
+int serial_init_dev (unsigned long dev_base)
+#else
+int serial_init(void)
+#endif
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
@@ -431,8 +432,18 @@ int serial_init (void)
 #endif
 
 #if defined(CONFIG_440_GX)
+#if defined(CONFIG_SERIAL_MULTI)
+	if (UART0_BASE == dev_base) {
+		mfsdr(UART0_SDR,reg);
+		reg &= ~CR0_MASK;
+	} else {
+		mfsdr(UART1_SDR,reg);
+		reg &= ~CR0_MASK;
+	}
+#else
 	mfsdr(UART0_SDR,reg);
 	reg &= ~CR0_MASK;
+#endif
 #else
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
 #endif /* CONFIG_440_GX */
@@ -451,11 +462,32 @@ int serial_init (void)
 
 #if defined(CONFIG_440_GX)
 	reg |= udiv << CR0_UDIV_POS;	/* set the UART divisor */
+#if defined(CONFIG_SERIAL_MULTI)
+	if (UART0_BASE == dev_base) {
+		mtsdr (UART0_SDR,reg);
+	} else {
+		mtsdr (UART1_SDR,reg);
+	}
+#else
 	mtsdr (UART0_SDR,reg);
+#endif
 #else
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
 #endif
+
+#if defined(CONFIG_SERIAL_MULTI)
+	out8 (dev_base + UART_LCR, 0x80);	/* set DLAB bit */
+	out8 (dev_base + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+	out8 (dev_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8 (dev_base + UART_FCR, 0x00);	/* disable FIFO */
+	out8 (dev_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8 (dev_base + UART_LSR);	/* clear line status */
+	val = in8 (dev_base + UART_RBR);	/* read receive buffer */
+	out8 (dev_base + UART_SCR, 0x00);	/* set scratchpad */
+	out8 (dev_base + UART_IER, 0x00);	/* set interrupt enable reg */
+#else
 	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
 	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
 	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
@@ -466,13 +498,17 @@ int serial_init (void)
 	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
 	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
 	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
-
+#endif
 	return (0);
 }
 
 #else /* !defined(CONFIG_440) */
 
+#if defined(CONFIG_SERIAL_MULTI)
+int serial_init_dev (unsigned long dev_base)
+#else
 int serial_init (void)
+#endif
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
@@ -517,6 +553,18 @@ int serial_init (void)
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
 
+#if defined(CONFIG_SERIAL_MULTI)