1. 29 Nov, 2006 6 commits
  2. 27 Nov, 2006 18 commits
  3. 23 Nov, 2006 1 commit
  4. 22 Nov, 2006 1 commit
  5. 20 Nov, 2006 3 commits
  6. 13 Nov, 2006 1 commit
  7. 12 Nov, 2006 2 commits
  8. 11 Nov, 2006 2 commits
  9. 10 Nov, 2006 1 commit
  10. 06 Nov, 2006 1 commit
  11. 04 Nov, 2006 4 commits
    • Timur Tabi's avatar
      mpc83xx: Update 83xx to use fsl_i2c.c · be5e6181
      Timur Tabi authored
      
      
      Update the 83xx tree to use I2C support in drivers/fsl_i2c.c.  Delete
      cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
      Added multiple I2C bus support to fsl_i2c.c.
      
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      be5e6181
    • Timur Tabi's avatar
      mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR · d239d74b
      Timur Tabi authored
      
      
      Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
      tree matches the other 8xxx trees.
      
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      d239d74b
    • Kim Phillips's avatar
      f7fb2e70
    • Dave Liu's avatar
      mpc83xx: Fix the incorrect dcbz operation · 90f30a71
      Dave Liu authored
      
      
      The 834x rev1.x silicon has one CPU5 errata.
      
      The issue is when the data cache locked with
      HID0[DLOCK], the dcbz instruction looks like no-op inst.
      
      The right behavior of the data cache is when the data cache
      Locked with HID0[DLOCK], the dcbz instruction allocates
      new tags in cache.
      
      The 834x rev3.0 and later and 8360 have not this bug inside.
      
      So, when 834x rev3.0/8360 are working with ECC, the dcbz
      instruction will corrupt the stack in cache, the processor will
      checkstop reset.
      
      However, the 834x rev1.x can work with ECC with these code,
      because the sillicon has this cache bug. The dcbz will not
      corrupt the stack in cache.
      Really, it is the fault code running on fault sillicon.
      
      This patch fix the incorrect dcbz operation. Instead of
      CPU FP writing to initialise the ECC.
      
      CHANGELOG:
      * Fix the incorrect dcbz operation instead of CPU FP
      writing to initialise the ECC memory. Otherwise, it
      will corrupt the stack in cache, The processor will checkstop
      reset.
      
      Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
      90f30a71