1. 12 Feb, 2009 1 commit
  2. 09 Feb, 2009 4 commits
  3. 03 Feb, 2009 2 commits
  4. 23 Jan, 2009 4 commits
  5. 22 Jan, 2009 1 commit
  6. 20 Dec, 2008 4 commits
  7. 16 Dec, 2008 1 commit
  8. 15 Dec, 2008 1 commit
    • Kumar Gala's avatar
      Introduce virt_to_phys() · 65e43a10
      Kumar Gala authored
      
      
      virt_to_phys() returns the physical address given a virtual. In most
      cases this will be just the input value as the vast majority of
      systems run in a 1:1 mode.
      
      However in systems that are not running this way it should report the
      physical address or ~0 if no mapping exists for the given virtual
      address.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      65e43a10
  9. 04 Dec, 2008 2 commits
  10. 21 Nov, 2008 1 commit
  11. 29 Oct, 2008 1 commit
  12. 27 Oct, 2008 1 commit
  13. 24 Oct, 2008 1 commit
  14. 21 Oct, 2008 3 commits
  15. 18 Oct, 2008 5 commits
  16. 17 Oct, 2008 3 commits
    • Yuri Tikhonov's avatar
      ppc4xx: PPC44x MQ initialization · bf29e0ea
      Yuri Tikhonov authored
      
      
      Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
      values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
      dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
      
      Previously the appropriate initialization had been made in Linux, by the
      ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
      registers after normal operation has begun is not supported and could
      have unpredictable results.
      
      Comment from Stefan: This patch doesn't change the resulting value of the
      MQ registers. It explicitly sets/clears all bits to the desired state which
      better documents the resulting register value instead of relying on pre-set
      default values.
      Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      bf29e0ea
    • Stefan Roese's avatar
      ppc4xx: PPC44x MQ initialization · ec081c2c
      Stefan Roese authored
      
      
      Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC
      values. This fixes the occasional 440SPe hard locking issues when the 440SPe's
      dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).
      
      Previously the appropriate initialization had been made in Linux, by the
      ppc440spe ADMA driver, which is wrong because modifying the MQ configuration
      registers after normal operation has begun is not supported and could
      have unpredictable results.
      
      Comment from Stefan: This patch doesn't change the resulting value of the
      MQ registers. It explicitly sets/clears all bits to the desired state which
      better documents the resulting register value instead of relying on pre-set
      default values.
      Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      ec081c2c
    • Kumar Gala's avatar
      85xx: Using proper I2C source clock divider for MPC8544 · f7d190b1
      Kumar Gala authored
      
      
      The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
      bit 26, instead it should be bit 28.  This caused in incorrect
      interpretation of the i2c_clk which is the same as the SEC clk on
      MPC8544.  The SEC clk is controlled by cfg_sec_freq that is reported
      in PORDEVSR2.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      f7d190b1
  17. 07 Oct, 2008 1 commit
  18. 22 Sep, 2008 1 commit
  19. 16 Sep, 2008 1 commit
  20. 08 Sep, 2008 1 commit
  21. 06 Sep, 2008 1 commit