1. 05 Oct, 2009 1 commit
  2. 02 Oct, 2009 3 commits
    • Matthias Fuchs's avatar
      ppc4xx: Add SDRAM detection for PMC440 boards · 3b4bd2d7
      Matthias Fuchs authored
      This patch adds support to detect the amount of DDR2 SDRAM
      on PMC440 modules. Detection is done by probing through
      a list of available and supported hardware configurations
      from 1GByte down to 256MB.
      The static TLB entry is replaced by dynamically created entries.
      Signed-off-by: default avatarMatthias Fuchs <matthias.fuchs@esd.eu>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
    • Stefan Roese's avatar
      ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling · fb95169e
      Stefan Roese authored
      This patch merges the ECC handling (ECC parity byte writing) into one
      file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
      This exception is because only those PPC's use the completely different
      Denali SDRAM controller core.
      Previously we had two routines to generate/write the ECC parity bytes.
      With this patch we now only have one core function left.
      Tested on Kilauea (no ECC) and Katmai (with and without ECC).
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Felix Radensky <felix@embedded-sol.com>
      Cc: Grant Erickson <gerickson@nuovations.com>
      Cc: Pieter Voorthuijsen <pv@prodrive.nl>
    • Felix Radensky's avatar
      ppc4xx: Reorganize DDR2 ECC handling · d24bd251
      Felix Radensky authored
      Reorganize DDR2 ECC handling to use common code for
      SPD DIMMs and soldered SDRAM. Also, use common code
      to display SDRAM info (ECC, CAS latency) for SPD and
      soldered SDRAM variants.
      Signed-off-by: default avatarFelix Radensky <felix@embedded-sol.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
  3. 30 Sep, 2009 6 commits
    • Mike Frysinger's avatar
      Blackfin: update default console= settings · 46a88794
      Mike Frysinger authored
      The Linux kernel has changed the way it numbers serial ports, so update
      the default command line to match it.
      Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
    • Mike Frysinger's avatar
      Blackfin: bf533-ezkit: update env location · 4c5f307d
      Mike Frysinger authored
      The u-boot image has outgrown the current space and overflowed into the
      env sector.  So move the env to the next available sector (we've already
      allocated the first few sectors anyways for u-boot).
      Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
    • Mingkai Hu's avatar
      On-chip ROM boot: MPC8536DS support · e40ac487
      Mingkai Hu authored
      The MPC8536E is capable of booting from the on-chip ROM - boot from
      eSDHC and boot from eSPI. When power on, the porcessor excutes the
      ROM code to initialize the eSPI/eSDHC controller, and loads the mian
      U-Boot image from the memory device that interfaced to the controller,
      such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
      L2SRAM, then boot from it.
      The memory device should contain a specific data structure with control
      word and config word at the fixed address. The config word direct the
      process how to config the memory device, and the control word direct
      the processor where to find the image on the memory device, or where
      copy the main image to. The user can use any method to store the data
      structure to the memory device, only if store it on the assigned address.
      The on-chip ROM code will map the whole 4GB address space by setting
      entry0 in the TLB1, so the main image need to switch to Address space 1
      to disable this mapping and map the address space again.
      This patch implements loading the mian U-Boot image into L2SRAM, so
      the image can configure the system memory by using SPD EEPROM.
      Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Mingkai Hu's avatar
      NAND boot: MPC8536DS support · 9a1a0aed
      Mingkai Hu authored
      MPC8536E can support booting from NAND flash which uses the
      image u-boot-nand.bin. This image contains two parts: a 4K
      NAND loader and a main U-Boot image. The former is appended
      to the latter to produce u-boot-nand.bin. The 4K NAND loader
      includes the corresponding nand_spl directory, along with the
      code twisted by CONFIG_NAND_SPL. The main U-Boot image just
      like a general U-Boot image except the parts that included by
      When power on, eLBC will automatically load from bank 0 the
      4K NAND loader into the FCM buffer RAM where CPU can execute
      the boot code directly. In the first stage, the NAND loader
      copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
      then loads the main image from NAND flash to RAM or L2SRAM
      and boot from it.
      This patch implements the NAND loader to load the main image
      into L2SRAM, so the main image can configure the RAM by using
      SPD EEPROM. In the first stage, the NAND loader copies itself
      to the second to last 4K address space, and uses the last 4K
      address space as the initial RAM for stack.
      Obviously, the size of L2SRAM shouldn't be less than the size
      of the image used. If so, the workaround is to generate another
      image that includes the code to configure the RAM by SPD and
      load it to L2SRAM first, then relocate the main image to RAM
      to boot up.
      Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Mingkai Hu's avatar
    • Paul Gortmaker's avatar
      sbc8548: reclaim wasted sector in boot flash · dd9ca98f
      Paul Gortmaker authored
      By nature of being based off the MPC8548CDS board, this
      board inherited an ENV_SIZE setting of 256k.  But since
      it has a smaller flash device (8MB soldered on), it has
      a native sector size of 128k, and hence the ENV_SIZE was
      causing 2 sectors to be used for the environment.
      By removing the unused sector, we can push TEXT_BASE up
      closer to the end of address space and reclaim that
      sector for any other application.  This also fixes the
      mismatch between TEXT_BASE and MONITOR_LEN reported by
      Kumar earlier.
      Since this board also supports the ability to boot off
      the 64MB SODIMM flash, this change is forward looking
      with that in mind; i.e. the settings for MONITOR_LEN
      and ENV_SIZE will work when the 512k sectors of the
      SODIMM flash are used for alternate boot in the future.
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  4. 29 Sep, 2009 1 commit
  5. 28 Sep, 2009 2 commits
  6. 27 Sep, 2009 1 commit
    • Kim Phillips's avatar
      mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields · c7190f02
      Kim Phillips authored
      some LCRR bits are not documented throughout the 83xx family RMs.
      New board porters copying similar board configurations might omit
      setting e.g., DBYP since it was not documented in their SoC's RM.
      Prevent them bricking their board by retaining power on reset values
      in bit fields that the board porter doesn't explicitly configure
      via CONFIG_SYS_<registername>_<bitfield> assignments in the board
      config file.
      also move LCRR assignment to cpu_init_r[am] to help ensure no
      transactions are being executed via the local bus while CLKDIV is being
      also start to use i/o accessors.
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
  7. 25 Sep, 2009 3 commits
  8. 24 Sep, 2009 23 commits