1. 16 Apr, 2015 1 commit
    • Kishon Vijay Abraham I's avatar
      ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.c · 4564faea
      Kishon Vijay Abraham I authored
      Commit d3cfcb3e
       (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY)
      changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl
      to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl
      to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between
      the two dwc3 controllers present in dra7xx/am43xx and enabled these
      clocks in enable_basic_clocks() in hw_data.c. However these clocks
      continued to be enabled in board files/driver files for dwc3 host
      mode functionality causing compilation break with few configs.
      Fixed it here by making all the clocks enabled in enable_basic_clocks()
      and removing it from board files/driver files here.
      Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
  2. 14 Apr, 2015 1 commit
  3. 29 Jan, 2015 1 commit
    • Lubomir Popov's avatar
      ARM: OMAP5: DRA7xx: Add support for power rail grouping · b558af81
      Lubomir Popov authored
      On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
      core rails. This concept of using one SMPS to supply multiple
      core domains (in various, although limited combinations, per
      primary device use case) has now become common and is used by
      many customer J6/J6Eco designs; it is supported by a number of
      corresponding PMIC OTP versions.
      This patch implements correct operation of the core voltages
      scaling routine by ensuring that each SMPS that is supplying
      more than one domain shall be written only once, and with the
      highest voltage of those fused in the SoC (or of those defined
      in the corresponding header if fuse read is disabled or fails)
      for the power rails belonging to the group.
      The patch also replaces some PMIC-related magic numbers with
      the appropriate definitions. The default OPP_NOM voltages for
      the DRA7xx SoCs are updated as well, per the latest DMs.
      Signed-off-by: default avatarLubomir Popov <l-popov@ti.com>
  4. 04 Dec, 2014 2 commits
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