1. 11 Jun, 2015 1 commit
  2. 18 May, 2015 1 commit
  3. 12 May, 2015 1 commit
  4. 18 Apr, 2015 2 commits
    • Masahiro Yamada's avatar
      dm: select CONFIG_DM* options · 58d423b8
      Masahiro Yamada authored
      As mentioned in the previous commit, adding default values in each
      Kconfig causes problems because it does not co-exist with the
      "depends on" syntax.  (Please note this is not a bug of Kconfig.)
      We should not do so unless we have a special reason.  Actually,
      for CONFIG_DM*, we have no good reason to do so.
      Generally, CONFIG_DM is not a user-configurable option.  Once we
      convert a driver into Driver Model, the board only works with Driver
      Model, i.e. CONFIG_DM must be always enabled for that board.
      So, using "select DM" is more suitable rather than allowing users to
      modify it.  Another good thing is, Kconfig warns unmet dependencies
      for "select" syntax, so we easily notice bugs.
      Actually, CONFIG_DM and other related options have been added
      without consistency: some into arch/*/Kconfig, some into
      board/*/Kconfig, and some into configs/*_defconfig.
      This commit prefers "select" and cleans up the following issues.
      [1] Never use "CONFIG_DM=n" in defconfig files
      It is really rare to add "CONFIG_FOO=n" to disable CONFIG options.
      It is more common to use "# CONFIG_FOO is not set".  But here, we
      do not even have to do it.
      Less than half of OMAP3 boards have been converted to Driver Model.
      Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is
      weird.  Instead, add "select DM" only to appropriate boards, which
      eventually eliminates "CONFIG_DM=n", etc.
      [2] Delete redundant CONFIGs
      Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again
      in configs/sandbox_defconfig.
      Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and
      defines it also in omap3_beagle_defconfig and devkit8000_defconfig.
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
    • Simon Glass's avatar
      dm: usb: exynos: Use driver model for USB · 874dde80
      Simon Glass authored
      Convert Exynos boards over to use driver model for USB. This does not remove
      any unnecessary code so far.
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
  5. 06 Apr, 2015 3 commits
  6. 28 Mar, 2015 2 commits
  7. 24 Mar, 2015 1 commit
    • Rob Herring's avatar
      remove unnecessary version.h includes · 7682a998
      Rob Herring authored
      Various files are needlessly rebuilt every time due to the version and
      build time changing. As version.h is not actually needed, remove the
      Signed-off-by: default avatarRob Herring <robh@kernel.org>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Minkyu Kang <mk7.kang@samsung.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Warren <twarren@nvidia.com>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: Macpaul Lin <macpaul@andestech.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: York Sun <yorksun@freescale.com>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Philippe Reynes <tremyfr@yahoo.fr>
      Cc: Eric Jarrige <eric.jarrige@armadeus.org>
      Cc: "David Müller" <d.mueller@elsoft.ch>
      Cc: Phil Edworthy <phil.edworthy@renesas.com>
      Cc: Robert Baldyga <r.baldyga@samsung.com>
      Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
      Cc: Anatolij Gustschin <agust@denx.de>
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Reviewed-by: default avatarŁukasz Majewski <l.majewski@samsung.com>
  8. 28 Feb, 2015 7 commits
    • Doug Anderson's avatar
      Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800 · 306f527e
      Doug Anderson authored
      It was found that the L2 cache timings that we had before could cause
      freezes and hangs.  We should make things more robust with better
      timings.  Currently the production ChromeOS kernel applies these
      timings, but it's nice to fixup firmware too (and upstream probably
      won't take our kernel hacks).
      This also provides a big cleanup of the L2 cache init code avoiding
      some duplication.  The way things used to work:
      * low_power_start() was installed by the SPL (both at boot and resume
        time) and left resident in iRAM for the kernel to use when bringing
        up additional CPUs.  It used configure_l2_ctlr() and
        configure_l2_actlr() when it detected it was on an A15.  This was
        needed (despite the L2 cache registers being shared among all A15s)
        because we might have been the first man in after the whole A15
        cluster was shutdown.
      * secondary_cores_configure() was called on at boot time and at resume
        time.  Strangely this called configure_l2_ctlr() but not
        configure_l2_actlr() which was almost certainly wrong.  Given that
        we'll call both (see next bullet) later in the boot process it
        didn't matter for normal boot, but I guess this is how L2 cache
        settings got set on 5420/5800 (but not 5250?) at resume time.
      * exynos5_set_l2cache_params() was called as part of cache enablement.
        This should happen at boot time (normally in the SPL except for USB
        boot where it happens in main U-Boot).
      Note that the old code wasn't setting ECC/parity in the cache
      enablement code but we happened to get it anyway because we'd call
      secondary_cores_configure() at boot time.  For resume time we'd get it
      anyway when the 2nd A15 core came up.
      Let's make this a whole lot simpler.  Now we always set these
      parameters in the same place for all boots and use the same code for
      setting up secondary CPUs.
      Intended net effects of this change (other than cleanup):
      * Timings go from before:
          data: 0 cycle setup, 3 cycles (0x2) latency
          tag:  0 cycle setup, 3 cycles (0x2) latency
          data: 1 cycle setup, 4 cycles (0x3) latency
          tag:  1 cycle setup, 4 cycles (0x3) latency
      * L2ACTLR is properly initted on 5420/5800 in all cases.
      One note is that we're still relying on luck to keep low_power_start()
      working.  The compiler is being nice and not storing anything on the
      Another note is that on its own this patch won't help to fix cache
      settings in an RW U-Boot update where we still have the RO SPL.  The
      plan for that is:
      * Have RW U-Boot re-init the cache right before calling the kernel
        (after it has turned the L2 cache off).  This is why the functions
        are in a header file instead of lowlevel_init.c.
      * Have the kernel save the L2 cache settings of the boot CPU and apply
        them to all other CPUs.  We get a little lucky here because the old
        code was using "|=" to modify the registers and all of the bits that
        it's setting are also present in the new settings (!).  That means
        that when the 2nd CPU in the A15 cluster comes up it doesn't
        actually mess up the settings of the 1st CPU in the A15 cluster.  An
        alternative option is to have the kernel write its own
        low_power_start() code.
      Signed-off-by: default avatarDoug Anderson <dianders@chromium.org>
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
    • Akshay Saraswat's avatar
      Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset · c8fd8e66
      Akshay Saraswat authored
      On warm reset, all cores jump to the low_power_start function because iRAM
      data is retained and because while executing iROM code all cores find
      the jump flag 0x02020028 set. In low_power_start, cores check the reset
      status and if true they clear the jump flag and jump back to 0x0.
      The A7 cores do jump to 0x0 but consider following instructions as a Thumb
      instructions which in turn makes them loop inside the iROM code instead of
      jumping to power_down_core.
      This issue is fixed by replacing the "mov pc" instruction with a "bx"
      instruction which switches state along with the jump to make the execution
      unit consider the branch target as an ARM instruction.
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
    • Akshay Saraswat's avatar
      Exynos542x: Fix secondary core booting for thumb · cecf2db2
      Akshay Saraswat authored
      When compiled SPL for Thumb secondary cores failed to boot
      at the kernel boot up. Only one core came up out of 4.
      This was happening because the code relocated to the
      address 0x02073000 by the primary core was an ARM asm
      code which was executed by the secondary cores as if it
      was a thumb code.
      This patch fixes the issue of secondary cores considering
      relocated code as Thumb instructions and not ARM instructions
      by jumping to the relocated with the help of "bx" ARM instruction.
      "bx" instruction changes the 5th bit of CPSR which allows
      execution unit to consider the following instructions as ARM
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
    • Akshay Saraswat's avatar
      Exynos542x: add L2 control register configuration · 7e514eef
      Akshay Saraswat authored
      This patch does 3 things:
      1. Enables ECC by setting 21st bit of L2CTLR.
      2. Restore data and tag RAM latencies to 3 cycles because iROM sets
         0x3000400 L2CTLR value during switching.
      3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
         We need to restore this here due to switching.
      Signed-off-by: default avatarAbhilash Kesavan <a.kesavan@samsung.com>
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
    • Akshay Saraswat's avatar
      Exynos542x: cache: Disable clean/evict push to external · f0f76b0a
      Akshay Saraswat authored
      L2 Auxiliary Control Register provides configuration
      and control options for the L2 memory system. Bit 3
      of L2ACTLR stands for clean/evict push to external.
      Setting bit 3 disables clean/evict which is what
      this patch intends to do.
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
    • Akshay Saraswat's avatar
      Exynos542x: Add workaround for exynos iROM errata · 67a0652c
      Akshay Saraswat authored
      iROM logic provides undesired jump address for CPU2.
      This patch adds a programmable susbstitute for a part of
      iROM logic which wakes up cores and provides jump addresses.
      This patch creates a logic to make all secondary cores jump
      to a particular address which evades the possibility of CPU2
      jumping to wrong address and create undesired results.
      Logic of the workaround:
      Step-1: iROM code checks value at address 0x2020028.
      Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4),
      	else, it continues executing normally.
      Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in
      	0x2020028 and jump address (pointer to function low_power_start)
      	in (0x202000+CPUid*4).
      Step-4: When secondary cores recieve event signal they jump to this address
      	and continue execution.
      Signed-off-by: default avatarKimoon Kim <kimoon.kim@samsung.com>
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
    • Akshay Saraswat's avatar
      Exynos542x: CPU: Power down all secondary cores · ac0d98cd
      Akshay Saraswat authored
      This patch adds code to shutdown secondary cores.
      When U-boot comes up, all secondary cores appear powered on,
      which is undesirable and causes side effects while
      initializing these cores in kernel.
      Secondary core power down happens in following steps:
      Step-1: After Exynos power-on, primary core starts executing first.
      Step-2: In iROM code every core has to check 2 flags i.e.
      	addresses 0x02020028 & 0x02020004.
      Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a
      	jump address for primary core and 0 for all secondary cores.
      Step-4: Therefore, primary core follows normal iROM execution and jumps
      	to BL1 eventually, whereas all secondary cores enter WFE.
      Step-5: When primary core comes into function secondary_cores_configure,
      	it puts pointer to function power_down_core into 0x02020004
      	and provides DSB and SEV for all cores so that they may come out
      	of WFE and jump to power_down_core function.
      Step-6: And ultimately because of power_down_core all
      	secondary cores shut-down.
      Signed-off-by: default avatarKimoon Kim <kimoon.kim@samsung.com>
      Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
      Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
  9. 24 Feb, 2015 1 commit
  10. 16 Feb, 2015 1 commit
  11. 13 Feb, 2015 9 commits
  12. 12 Feb, 2015 2 commits
  13. 30 Jan, 2015 1 commit
  14. 24 Dec, 2014 1 commit
  15. 22 Dec, 2014 1 commit
  16. 24 Nov, 2014 1 commit
  17. 23 Nov, 2014 1 commit
  18. 17 Nov, 2014 4 commits