1. 21 Jul, 2015 2 commits
    • Simon Glass's avatar
      dm: pci: Add a function to get the BDF for a device · 4b515e4f
      Simon Glass authored
      
      
      It is useful to be able to find the full PCI address (bus, device and
      function) for a PCI device. Add a function to provide this.
      
      Adjust the existing code to use this.
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      4b515e4f
    • Simon Glass's avatar
      dm: pci: Add support for PCI driver matching · aba92962
      Simon Glass authored
      
      
      At present all PCI devices must be present in the device tree in order to
      be used. Many or most PCI devices don't require any configuration other than
      that which is done automatically by U-Boot. It is inefficent to add a node
      with nothing but a compatible string in order to get a device working.
      
      Add a mechanism whereby PCI drivers can be declared along with the device
      parameters they support (vendor/device/class). When no suitable driver is
      found in the device tree the list of such devices is consulted to determine
      the correct driver. If this also fails, then a generic driver is used as
      before.
      
      The mechanism used is very similar to that provided by Linux and the header
      file defintions are copied from Linux 4.1.
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      Reviewed-by: default avatarJoe Hershberger <joe.hershberger@ni.com>
      aba92962
  2. 15 Jul, 2015 2 commits
  3. 17 Apr, 2015 3 commits
  4. 06 Feb, 2015 1 commit
  5. 24 Jan, 2015 1 commit
  6. 05 Jan, 2015 1 commit
  7. 25 Nov, 2014 1 commit
  8. 23 Nov, 2014 1 commit
    • Thierry Reding's avatar
      pci: Honour pci_skip_dev() · 4efe52bf
      Thierry Reding authored
      
      
      When enumerating devices, honour the pci_skip_dev() function. This can
      be used by PCI controller drivers to restrict which devices will be
      probed.
      
      This is required by the NVIDIA Tegra PCIe controller driver, which will
      fail with a data abort exception if an access is attempted to a device
      number larger than 0 outside of bus 0. pci_skip_dev() is therefore
      implemented to prevent any such accesses.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      4efe52bf
  9. 09 Sep, 2014 1 commit
  10. 09 Nov, 2013 1 commit
  11. 16 Oct, 2013 1 commit
    • Zhao Qiang's avatar
      PCIe:change the method to get the address of a requested capability in configuration space. · 287df01e
      Zhao Qiang authored
      
      
      Previously, the address of a requested capability is define like that
      	"#define PCI_DCR	0x78"
      But, the addresses of capabilities is different with regard to PCIe revs.
      So this method is not flexible.
      
      Now a function to get the address of a requested capability is added and used.
      It can get the address dynamically by capability ID.
      The step of this function:
      	1. Read Status register in PCIe configuration space to confirm that
      	   Capabilities List is valid.
      	2. Find the address of Capabilities Pointer Register.
      	3. Find the address of requested capability from the first capability.
      Signed-off-by: default avatarZhao Qiang <B45475@freescale.com>
      287df01e
  12. 09 Aug, 2013 1 commit
    • Zang Roy-R61911's avatar
      powerpc/pcie: add PCIe version 3.x support · 7b4e5844
      Zang Roy-R61911 authored
      
      
      T4240 PCIe IP is version 3.0 and has some update comparing previous
      QorIQ products.
      
      1.  Move Freescale specific register define
      to
      arch/powerpc/include/asm/fsl_pci.h
      and update the register offset define for T4240.
      
      2. add the status/control register define
      use status/control register to judge the link status
      
      3. The original code uses 'Programming Interface' field to judge if PCIE is
      EP or RC mode, however, T4240 does not support this functionality.
      According to PCIE specification, 'Header Type' offset 0x0e is used to
      indicate header type, so for PCIE controller, the patch changes code to
      use 'Header Type' field to identify if the PCIE is RC or EP mode.
      
      This patch fixes  the PCIe card link up issue on T4240QDS.
      Signed-off-by: default avatarRoy Zang <tie-fei.zang@freescale.com>
      Signed-off-by: default avatarMinghuan Lian <Minghuan.Lian@freescale.com>
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      7b4e5844
  13. 24 Jul, 2013 1 commit
  14. 26 Jun, 2013 1 commit
  15. 07 Jun, 2013 1 commit
    • Gabor Juhos's avatar
      pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option · 842033e6
      Gabor Juhos authored
      
      
      The pci_indirect.c file is always compiled when
      CONFIG_PCI is defined although the indirect PCI
      bridge support is not needed by every board.
      
      Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
      config option and only compile indirect PCI
      bridge support if this options is enabled.
      
      Also add the new option into the configuration
      files of the boards which needs that.
      
      Compile tested for powerpc, x86, arm and nds32.
      MAKEALL results:
      
      powerpc:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 641
        Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
        ----------------------------------------------------------
        Note: the warnings for ELPPC and MPC8323ERDB are present even
        without the actual patch.
      
      x86:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 1
        ----------------------------------------------------------
      
      arm:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 311
        ----------------------------------------------------------
      
      nds32:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 3
        ----------------------------------------------------------
      
      Cc: Tom Rini <trini@ti.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
      Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
      842033e6
  16. 06 Dec, 2012 1 commit
  17. 30 Mar, 2012 1 commit
  18. 04 Mar, 2012 1 commit
    • Linus Walleij's avatar
      pci: move pciauto_config_init() to pci.h · a1e47b66
      Linus Walleij authored
      
      
      Fixing build regressions for the Integrator I get find that a few
      boards try to work around the missing declaration of
      pciauto_config_init() by declaring it in the local scope. This
      does not make sense when the sibling functions are in <pci.h>
      so move the function to the header, ridding the build error
      in the Integrator and getting rid of the local declarations
      here and there.
      Reported-by: default avatarWolfgang Denk <wd@denx.de>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      a1e47b66
  19. 29 Mar, 2011 1 commit
  20. 05 Feb, 2011 1 commit
  21. 14 Jan, 2011 1 commit
  22. 14 Nov, 2010 1 commit
    • Peter Tyser's avatar
      pci: Clean up PCI info when CONFIG_PCI_SCAN_SHOW · 983eb9d1
      Peter Tyser authored
      
      
      This change does the following:
      - Removes the printing of the PCI interrupt line value.  This is
        normally set to 0 by U-Boot on bootup and is rarely used during
        everyday operation.
      
      - Prints out the PCI function number of a device.  Previously a device
        with multiple functions would be printed identically 2 times, which is
        generally confusing.  For example, on an Intel 2 port gigabit Ethernet
        card the following was displayed:
          ...
          04  01  8086  1010  0200  00
          04  01  8086  1010  0200  00
          ...
      
      - Prints a text description of each device's PCI class instead of the
        raw PCI class code.  The textual description makes it much easier to
        determine what devices are installed on a PCI bus.
      
      - Changes the general formatting of the PCI device output.
      
      Previous output:
        PCIE1: connected as Root Complex
                04  01  8086  1010  0200  00
                04  01  8086  1010  0200  00
                03  00  10b5  8112  0604  00
                02  01  10b5  8518  0604  00
                02  02  10b5  8518  0604  00
                08  00  1957  0040  0b20  00
                07  00  10b5  8518  0604  00
                09  00  10b5  8112  0604  00
                07  01  10b5  8518  0604  00
                07  02  10b5  8518  0604  00
                06  00  10b5  8518  0604  00
                02  03  10b5  8518  0604  00
                01  00  10b5  8518  0604  00
        PCIE1: Bus 00 - 0b
        PCIE2: connected as Root Complex
                0d  00  1957  0040  0b20  00
        PCIE2: Bus 0c - 0d
      
      Updated output:
        PCIE1: connected as Root Complex
                04:01.0 - 8086:1010 - Network controller
                04:01.1 - 8086:1010 - Network controller
                03:00.0 - 10b5:8112 - Bridge device
                02:01.0 - 10b5:8518 - Bridge device
                02:02.0 - 10b5:8518 - Bridge device
                08:00.0 - 1957:0040 - Processor
                07:00.0 - 10b5:8518 - Bridge device
                09:00.0 - 10b5:8112 - Bridge device
                07:01.0 - 10b5:8518 - Bridge device
                07:02.0 - 10b5:8518 - Bridge device
                06:00.0 - 10b5:8518 - Bridge device
                02:03.0 - 10b5:8518 - Bridge device
                01:00.0 - 10b5:8518 - Bridge device
        PCIE1: Bus 00 - 0b
        PCIE2: connected as Root Complex
                0d:00.0 - 1957:0040 - Processor
        PCIE2: Bus 0c - 0d
      Signed-off-by: default avatarPeter Tyser <ptyser@xes-inc.com>
      983eb9d1
  23. 28 Aug, 2009 1 commit
  24. 23 Feb, 2009 1 commit
  25. 09 Feb, 2009 1 commit
  26. 07 Feb, 2009 1 commit
  27. 22 Jan, 2009 1 commit
  28. 24 Oct, 2008 1 commit
  29. 09 May, 2008 1 commit
  30. 05 Aug, 2007 1 commit
  31. 19 Oct, 2006 1 commit
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  33. 09 Aug, 2006 1 commit
  34. 28 Jun, 2006 1 commit
  35. 26 Apr, 2006 1 commit
  36. 12 Mar, 2006 1 commit