- 16 Aug, 2016 8 commits
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Stefan Roese authored
This simple driver provides some functions to control some of the integrated devices. The watchdog is enabled per default. This driver adds a function to disable the watchdog. Also the internal legacy UART (io address 0x3f8/0x2f8) is enabled per default. Signed-off-by:
Stefan Roese <sr@denx.de> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
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Stefan Roese authored
To support the BayTrail internal SIO HS UART, the internal UART clock needs to get configured. This patch adds support for this clock configuration which will be done, if the PCI device(s) are found. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Stefan Roese authored
Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE if it's undefined. This is needed for the xhci driver to compile. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
This feature is not supported. Document this, and add some details on how it might be implemented. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
UEFI is commonly used on x86. Add a reference to U-Boot's support for this in the x86 README. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
The README indicates that this is not supported, but this is no-longer true. Update the text to indicate this and describe the FIT changes required. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Stefan Roese authored
The debug FSP image is bigger in size than the normal FSP image. This patch adds a small description on how to use this FSP debug version by changing CONFIG_FSP_ADDR. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Stefan Roese authored
Add entry for the missing internal UART defconfig to the MAINTAINERS file. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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- 15 Aug, 2016 32 commits
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Tom Rini authored
Now that nand_info[] is an array of pointers we need to ensure that it's been populated prior to use. We may for example have ENV in NAND set in configurations that run on boards with and without NAND (where default env is fine enough, such as omap3_beagle and beagleboard (NAND) vs beagle xM (no NAND)). Fixes: b616d9b0 ("nand: Embed mtd_info in struct nand_chip") Cc: Scott Wood <oss@buserror.net> Signed-off-by:
Tom Rini <trini@konsulko.com> Acked-by:
Scott Wood <oss@buserror.net>
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Andreas Fenkart authored
56086921 added support for unaligned environments access. U-boot itself does not support this: - env_nand.c fails when using an unaligned offset. It produces an error in nand_erase_opts{drivers/mtd/nand/nand_util.c} - in env_sf/env_flash the unused space at the end is preserved, but not in the beginning. block alignment is assumed - env_sata/env_mmc aligns offset/length to the block size of the underlying device. data is silently redirected to the beginning of a block There is seems no use case for unaligned environment. If there is some useful data at the beginning of the the block (e.g. end of u-boot) that would be very unsafe. If the redundant environments are hosted by the same erase block then that invalidates the idea of double buffering. It might be that unaligned access was allowed in the past, and that people with legacy u-boot are trapped. But at the time of 56086921 it wasn't supported and due to reasons above I guess it was never introduced. I prefer to remove that (unused) feature in favor of simplicity Signed-off-by:
Andreas Fenkart <andreas.fenkart@digitalstrom.com> Acked-by:
Stefan Agner <stefan.agner@toradex.com>
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Chris Zankel authored
The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by:
Chris Zankel <chris@zankel.net> Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Max Filippov authored
DE212 is a general purpose xtensa processor without full MMU. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Max Filippov authored
DC233C is an xtensa processor with full MMUv3 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Chris Zankel authored
DC232B is an xtensa processor with full MMUv2 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by:
Chris Zankel <chris@zankel.net> Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Chris Zankel authored
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by:
Chris Zankel <chris@zankel.net> Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Chris Zankel authored
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by:
Chris Zankel <chris@zankel.net> Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Jon Medhurst \(Tixy\) authored
The firmware on TC2 needs to be configured appropriately before booting in nonsec mode will work as expected, so test for this and fall back to sec mode if required. Signed-off-by:
Jon Medhurst <tixy@linaro.org> Reviewed-by:
Ryan Harkin <ryan.harkin@linaro.org> Tested-by:
Ryan Harkin <ryan.harkin@linaro.org>
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git://git.denx.de/u-boot-atmelTom Rini authored
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Wenyou Yang authored
Convert the driver to the driver model while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by:
Heiko Schocher <hs@denx.de>
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Wenyou Yang authored
Add driver model support while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Wenyou Yang authored
Add device tree for SAMA5D2 Xplained board. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com>
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Wenyou Yang authored
Bring in required device tree file and bindings from Linux. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Wenyou Yang authored
AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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Wenyou Yang authored
Rework the driver to support driver model and device tree, and support to regard the pio4 pinctrl device as a child of atmel_pio4 device. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Wenyou Yang authored
In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Andreas Bießmann authored
Fix compile warning for non OF_CONTROL builds: ---8<--- In file included from /Volumes/devel/u-boot/drivers/gpio/atmel_pio4.c:10:0: /Volumes/devel/u-boot/include/clk.h:107:12: warning: 'clk_get_by_name' defined but not used [-Wunused-function] --->8--- Signed-off-by:
Andreas Bießmann <andreas@biessmann.org> Acked-by:
Stephen Warren <swarren@nvidia.com>
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git://git.denx.de/u-boot-netTom Rini authored
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Joe Hershberger authored
The cleanup of the legacy mii registration API that's no longer used now that the drivers have been converted to use the (more) modern API. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Joe Hershberger authored
If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by:
Stefan Roese <sr@denx.de> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Joe Hershberger authored
Some of the changes were a bit too complex. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Joe Hershberger authored
Run scripts/coccinelle/net/mdio_register.cocci on the U-Boot code base. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Joe Hershberger authored
Many Ethernet drivers still use the legacy miiphy API to register their mdio interface for access to the mdio commands. This semantic patch will convert the drivers from the legacy adapter API to the more modern alloc/register API. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com>
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Wenyou Yang authored
The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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mario.six@gdsys.cc authored
Commit 302c5dba ("dm: tpm: Add Driver Model support for tpm_atmel_twi driver") converted the Atmel TWI TPM driver itself to driver model, but kept the legacy-style i2c_write/i2c_read calls. Commit 3e7d940b ("dm: tpm: Every TPM drivers should depends on DM_TPM") then made DM_I2C a dependency of the driver, effectively forcing users to turn on CONFIG_DM_I2C_COMPAT to get it to work. This patch adds the necessary dm_i2c_write/dm_i2c_read calls to make the driver compatible with DM, but also keeps the legacy calls in ifdefs, so that the driver is now compatible with both DM and non-DM setups. Signed-off-by:
Mario Six <mario.six@gdsys.cc> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org>
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Songjun Wu authored
DT binding documentation for atmel i2c driver. Signed-off-by:
Songjun Wu <songjun.wu@atmel.com> Reviewed-by:
Heiko Schocher <hs@denx.de> Acked-by:
Heiko Schocher <hs@denx.de>
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Songjun Wu authored
Add i2c driver. Signed-off-by:
Songjun Wu <songjun.wu@atmel.com> Reviewed-by:
Heiko Schocher <hs@denx.de> Acked-by:
Heiko Schocher <hs@denx.de>
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Max Filippov authored
Implement MDIO bus read/write functions, initialize the bus and scan for the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps. Cc: Michal Simek <monstr@monstr.eu> Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Max Filippov authored
The ethoc device can be configured to have a private memory region instead of having access to the main memory. In that case egress packets must be copied into that memory for transmission and pointers to that memory need to be passed to net_process_received_packet or returned from the recv callback. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Max Filippov authored
Addresses used in buffer descriptors and passed in platform data or device tree are physical. Addresses used by CPU to access packet data and registers are virtual. Don't mix these addresses and use virt_to_phys for translation. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Max Filippov authored
Add .of_match table and .ofdata_to_platdata callback to allow for ethoc device configuration from the device tree. Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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