1. 07 May, 2015 2 commits
  2. 05 May, 2015 1 commit
  3. 29 Apr, 2015 1 commit
  4. 21 Apr, 2015 1 commit
  5. 28 Mar, 2015 1 commit
  6. 13 Mar, 2015 1 commit
    • Nishanth Menon's avatar
      ARM: Introduce erratum workaround for 798870 · c616a0df
      Nishanth Menon authored
      
      
      Add workaround for Cortex-A15 ARM erratum 798870 which says
      "If back-to-back speculative cache line fills (fill A and fill B) are
      issued from the L1 data cache of a CPU to the L2 cache, the second
      request (fill B) is then cancelled, and the second request would have
      detected a hazard against a recent write or eviction (write B) to the
      same cache line as fill B then the L2 logic might deadlock."
      
      Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
      will be widely different.
      
      Every SoC has slightly different manner of setting up access to L2ACLR
      and similar registers since the Secure Monitor handling of Secure
      Monitor Call(smc) is diverse. Hence an weak function is introduced
      which may be overriden to implement SoC specific accessor implementation.
      
      Based on ARM errata Document revision 18.0 (22 Nov 2013)
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Tested-by: default avatarMatt Porter <mporter@konsulko.com>
      Reviewed-by: default avatarTom Rini <trini@konsulko.com>
      c616a0df
  7. 28 Feb, 2015 1 commit
  8. 21 Feb, 2015 5 commits
    • Stephen Warren's avatar
      bcm2836 SoC support (used in Raspberry Pi 2 model B) · db75356f
      Stephen Warren authored
      
      
      The bcm2835 and bcm2836 are essentially identical, except:
      - The CPU is an ARM1176 v.s. a quad-core Cortex-A7.
      - The physical address of many IO controllers has moved.
      
      Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH),
      update the existing bcm2835 code to handle the minor differences, and
      plumb it into the ARMv7 CPU architecture.
      Signed-off-by: default avatarStephen Warren <swarren@wwwdotorg.org>
      db75356f
    • Masahiro Yamada's avatar
      ARM: keystone: move SoC sources to mach-keystone · 39a72345
      Masahiro Yamada authored
      
      
      Move
      arch/arm/cpu/armv7/keystone/* -> arch/arm/mach-keystone/*
      Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
      Cc: Tom Rini <trini@ti.com>
      39a72345
    • Masahiro Yamada's avatar
      ARM: highbank: move SoC sources to mach-highbank · 72a8ff4b
      Masahiro Yamada authored
      
      
      Move
      arch/arm/cpu/armv7/highbank/* -> arch/arm/mach-highbank/*
      Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
      Cc: Rob Herring <robh@kernel.org>
      72a8ff4b
    • Masahiro Yamada's avatar
      ARM: tegra: collect SoC sources into mach-tegra · 09f455dc
      Masahiro Yamada authored
      
      
      This commit moves files as follows:
      
       arch/arm/cpu/arm720t/tegra20/*      -> arch/arm/mach-tegra/tegra20/*
       arch/arm/cpu/arm720t/tegra30/*      -> arch/arm/mach-tegra/tegra30/*
       arch/arm/cpu/arm720t/tegra114/*     -> arch/arm/mach-tegra/tegra114/*
       arch/arm/cpu/arm720t/tegra124*      -> arch/arm/mach-tegra/tegra124/*
       arch/arm/cpu/arm720t/tegra-common/* -> arch/arm/mach-tegra/*
       arch/arm/cpu/armv7/tegra20/*        -> arch/arm/mach-tegra/tegra20/*
       arch/arm/cpu/armv7/tegra30/*        -> arch/arm/mach-tegra/tegra30/*
       arch/arm/cpu/armv7/tegra114/*       -> arch/arm/mach-tegra/tegra114/*
       arch/arm/cpu/armv7/tegra124/*       -> arch/arm/mach-tegra/tegra124/*
       arch/arm/cpu/armv7/tegra-common/*   -> arch/arm/mach-tegra/*
       arch/arm/cpu/tegra20-common/*       -> arch/arm/mach-tegra/tegra20/*
       arch/arm/cpu/tegra30-common/*       -> arch/arm/mach-tegra/tegra30/*
       arch/arm/cpu/tegra114-common/*      -> arch/arm/mach-tegra/tegra114/*
       arch/arm/cpu/tegra124-common/*      -> arch/arm/mach-tegra/tegra124/*
       arch/arm/cpu/tegra-common/*         -> arch/arm/mach-tegra/*
      Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
      Tested-by: Simon Glass <sjg@chromium.org> [ on nyan-big ]
      Cc: Stephen Warren <swarren@nvidia.com>
      Cc: Tom Warren <twarren@nvidia.com>
      09f455dc
    • Masahiro Yamada's avatar
      ARM: at91: collect SoC sources into mach-at91 · 62011840
      Masahiro Yamada authored
      
      
      This commit moves source files as follows:
      
        arch/arm/cpu/arm920t/at91/*   -> arch/arm/mach-at91/arm920t/*
        arch/arm/cpu/arm926ejs/at91/* -> arch/arm/mach-at91/arm926ejs/*
        arch/arm/cpu/armv7/at91/*     -> arch/arm/mach-at91/armv7/*
        arch/arm/cpu/at91-common/*    -> arch/arm/mach-at91/*
      Signed-off-by: default avatarMasahiro Yamada <yamada.m@jp.panasonic.com>
      Acked-by: default avatarAndreas Bießmann <andreas.devel@googlemail.co>
      62011840
  9. 09 Dec, 2014 1 commit
  10. 23 Nov, 2014 3 commits
  11. 30 Aug, 2014 1 commit
  12. 28 Jul, 2014 2 commits
  13. 25 May, 2014 1 commit
  14. 17 Apr, 2014 1 commit
  15. 22 Feb, 2014 1 commit
  16. 01 Dec, 2013 1 commit
  17. 31 Oct, 2013 4 commits
  18. 03 Oct, 2013 3 commits
    • Andre Przywara's avatar
      ARM: extend non-secure switch to also go into HYP mode · d4296887
      Andre Przywara authored
      
      
      For the KVM and XEN hypervisors to be usable, we need to enter the
      kernel in HYP mode. Now that we already are in non-secure state,
      HYP mode switching is within short reach.
      
      While doing the non-secure switch, we have to enable the HVC
      instruction and setup the HYP mode HVBAR (while still secure).
      
      The actual switch is done by dropping back from a HYP mode handler
      without actually leaving HYP mode, so we introduce a new handler
      routine in our new secure exception vector table.
      
      In the assembly switching routine we save and restore the banked LR
      and SP registers around the hypercall to do the actual HYP mode
      switch.
      
      The C routine first checks whether we are in HYP mode already and
      also whether the virtualization extensions are available. It also
      checks whether the HYP mode switch was finally successful.
      The bootm command part only calls the new function after the
      non-secure switch.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@linaro.org>
      d4296887
    • Andre Przywara's avatar
      ARM: add C function to switch to non-secure state · 1ef92385
      Andre Przywara authored
      
      
      The core specific part of the work is done in the assembly routine
      in nonsec_virt.S, introduced with the previous patch, but for the full
      glory we need to setup the GIC distributor interface once for the
      whole system, which is done in C here.
      The routine is placed in arch/arm/cpu/armv7 to allow easy access from
      other ARMv7 boards.
      
      We check the availability of the security extensions first.
      
      Since we need a safe way to access the GIC, we use the PERIPHBASE
      registers on Cortex-A15 and A7 CPUs and do some sanity checks.
      Boards not implementing the CBAR can override this value via a
      configuration file variable.
      
      Then we actually do the GIC enablement:
      a) enable the GIC distributor, both for non-secure and secure state
         (GICD_CTLR[1:0] = 11b)
      b) allow all interrupts to be handled from non-secure state
         (GICD_IGROUPRn = 0xFFFFFFFF)
      
      The core specific GIC setup is then done in the assembly routine.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@linaro.org>
      1ef92385
    • Andre Przywara's avatar
      ARM: add secure monitor handler to switch to non-secure state · 45b940d6
      Andre Przywara authored
      
      
      A prerequisite for using virtualization is to be in HYP mode, which
      requires the CPU to be in non-secure state first.
      Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
      which switches the CPU to non-secure state by setting the NS and
      associated bits.
      According to the ARM architecture reference manual this should not be
      done in SVC mode, so we have to setup a SMC handler for this.
      We create a new vector table to avoid interference with other boards.
      The MVBAR register will be programmed later just before the smc call.
      Signed-off-by: default avatarAndre Przywara <andre.przywara@linaro.org>
      45b940d6
  19. 15 Aug, 2013 2 commits
  20. 24 Jul, 2013 1 commit
  21. 24 Mar, 2013 1 commit
  22. 07 Mar, 2013 1 commit
  23. 16 Jan, 2013 1 commit
  24. 01 Sep, 2012 2 commits
  25. 27 Mar, 2012 1 commit