1. 07 May, 2015 2 commits
  2. 21 Apr, 2015 3 commits
  3. 18 Apr, 2015 1 commit
  4. 04 Mar, 2015 2 commits
  5. 12 Feb, 2015 1 commit
  6. 21 Dec, 2014 1 commit
    • Stefan Roese's avatar
      arm: socfpga: Change watchdog timeout · d0e932de
      Stefan Roese authored
      
      
      The current current watchdog timeout of 12 seconds is a bit small for
      booting into Linux, especially when using a NFS based rootfs. So lets
      change this timeout to a more defensive value of 30 seconds.
      
      Also we now call the hw_watchdog_init() function so that we override
      the value already configured from the Preloader.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Vince Bridgers <vbridger@opensource.altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      d0e932de
  7. 06 Dec, 2014 3 commits
    • Stefan Roese's avatar
      arm: socfpga: DW_SPI: Remove clock info from config header · 0edeba05
      Stefan Roese authored
      
      
      Remove the now unnecessary clocking info from the SoCFPGA
      config header. As this info in now used directly in the SPI driver
      itself.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      0edeba05
    • Stefan Roese's avatar
      arm: socfpga: Add Designware (DW) SPI support to config header · a6e73591
      Stefan Roese authored
      
      
      Enable support for the DW master SPI controller in the config header
      for the SoCFPGA. This controller can only be enabled, if DT support
      is enabled.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      a6e73591
    • Stefan Roese's avatar
      arm: socfpga: Add Cadence QSPI support to config header · 7fb0f596
      Stefan Roese authored
      
      
      With this driver enabled for SoCFPGA, access to SPI NOR flash is
      supported.
      
      The configuration (page size, timing info) will be taken from the
      DT. See socrates as an example.
      
      This QSPI supports depends on DT. So QSPI is only enabled if
      CONFIG_OF_CONTROL is defined (see socfpga_socrates_defconfig).
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
      7fb0f596
  8. 20 Nov, 2014 1 commit
  9. 07 Nov, 2014 1 commit
  10. 31 Oct, 2014 1 commit
  11. 30 Oct, 2014 1 commit
    • Stefan Roese's avatar
      arm: socfpga: Add I2C support to SoCFPGA · ebcaf966
      Stefan Roese authored
      
      
      This patch adds I2C support for the SoCFPGA. Using the designware I2C
      controller driver. It supports all 4 I2C busses on the SoCFPGA.
      
      The designware I2C driver has now been converted to the
      CONFIG_SYS_I2C framework. So lets enable it on SoCFPGA.
      
      Tested on SoCrates.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Heiko Schocher <hs@denx.de>
      ebcaf966
  12. 27 Oct, 2014 3 commits
  13. 06 Oct, 2014 10 commits
    • Pavel Machek's avatar
      arm: socfpga: Split SoCFPGA configuration · 5095ee08
      Pavel Machek authored
      
      
      Split the SoCFPGA configuration into SoC-specific part which is
      common for all boards (socfpga_cyclone5_common.h) and a board
      specific part. There is currently only one board, which is the
      generic SoCFPGA board (socfpga_cyclone5.h), but there are more
      to come.
      
      This is necessary due to various features of the boards, which
      unfortunatelly cannot be autodetected.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      5095ee08
    • Marek Vasut's avatar
      arm: socfpga: Clean up SoCFPGA configuration · 47f9b4e1
      Marek Vasut authored
      
      
      Reorganize and cleanup the configuration file for SoCFPGA. There
      is no functional change after this cleanup. This was necessary,
      since the file was a wild mess and it was impossible to make sense
      of it's content, let alone change something without breaking some
      other thing. This patch puts the contents on par with regular U-Boot
      standards.
      
      Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
      and CONFIG_USE_IRQ, which is undefined by default. Finally, do
      logical reordering of the defines in the file so it's much more
      readable. The reordering was also necessary for the splitting
      as the initial one was messy.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      47f9b4e1
    • Chin Liang See's avatar
      arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot · 97ce274d
      Chin Liang See authored
      
      
      Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
      Enable the bootz command as zImage is used instead uImage.
      Signed-off-by: default avatarChin Liang See <clsee@altera.com>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      97ce274d
    • Chin Liang See's avatar
      arm: socfpga: Enable DWMMC for SOCFPGA · ddcbed04
      Chin Liang See authored
      
      
      Enable the DesignWare MMC controller driver support
      for SOCFPGA Cyclone5 dev kit
      Signed-off-by: default avatarChin Liang See <clsee@altera.com>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Wolfgang Denk <wd@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      ddcbed04
    • Marek Vasut's avatar
      arm: socfpga: cache: Enable PL310 L2 cache · b5e9b296
      Marek Vasut authored
      
      
      Enable the PL310 L2 cache controller support for the SoCFPGA.
      With the cache related issues resolved, this is safe to be done.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      b5e9b296
    • Marek Vasut's avatar
      arm: socfpga: cache: Enable D-Cache · 40e7bcde
      Marek Vasut authored
      
      
      The code is now fixed to the point where we can safely enable
      the L1 data cache. Enable the D-Cache and set it as write-alloc.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      40e7bcde
    • Marek Vasut's avatar
      arm: socfpga: cache: Define cacheline size · 9ca2116c
      Marek Vasut authored
      
      
      The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      9ca2116c
    • Marek Vasut's avatar
      arm: socfpga: timer: Pull the timer reload value from config file · 2110eeaf
      Marek Vasut authored
      
      
      The timer reload value is a property of the timer hardware and there
      is no reason for this to be configurable. Place this into the timer
      driver just like on the other hardware.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Acked-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      Acked-by: default avatarPavel Machek <pavel@denx.de>
      2110eeaf
    • Pavel Machek's avatar
      arm: socfpga: clock: Add code to read clock configuration · a832ddba
      Pavel Machek authored
      
      
      Add the entire bulk of code to read out clock configuration from the SoCFPGA
      CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
      they cannot determine the frequency of their upstream clock.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      
      V2: Fixed the L4 MP clock divider and synced the clock code with latest
          rocketboards codebase (thanks Dinh for pointing this out)
      a832ddba
    • Pavel Machek's avatar
      net: Remove unused CONFIG_DW_SEARCH_PHY from configs · 464eec6d
      Pavel Machek authored
      
      
      Remove this symbol from configs, since it's unused.
      Signed-off-by: default avatarPavel Machek <pavel@denx.de>
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Tom Rini <trini@ti.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Joe Hershberger <joe.hershberger@gmail.com>
      Acked-by: default avatarChin Liang See <clsee@altera.com>
      464eec6d
  14. 30 Aug, 2014 1 commit
  15. 29 Aug, 2014 1 commit
    • Chin Liang See's avatar
      socfpga: Fix SOCFPGA build error for Altera dev kit · 3ab019e1
      Chin Liang See authored
      
      
      To fix the build error when build for Altera dev kit, not
      virtual target. At same time, set the build for Altera dev
      kit as default instead virtual target. With that, U-Boot
      is booting well and SPL still lack of few drivers.
      Signed-off-by: default avatarChin Liang See <clsee@altera.com>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      3ab019e1
  16. 30 Jul, 2014 2 commits
  17. 14 Jul, 2014 1 commit
  18. 04 Jul, 2014 2 commits
  19. 07 Apr, 2014 1 commit
  20. 15 Nov, 2013 1 commit
  21. 04 Nov, 2013 1 commit