1. 06 Dec, 2008 1 commit
  2. 18 Oct, 2008 1 commit
  3. 17 Oct, 2008 1 commit
  4. 03 Sep, 2008 3 commits
  5. 12 Aug, 2008 1 commit
    • Scott Wood's avatar
      NAND boot: MPC8313ERDB support · e4c09508
      Scott Wood authored
      
      
      Note that with older board revisions, NAND boot may only work after a
      power-on reset, and not after a warm reset.  I don't have a newer board
      to test on; if you have a board with a 33MHz crystal, please let me know
      if it works after a warm reset.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      e4c09508
  6. 03 Jun, 2008 1 commit
    • Becky Bruce's avatar
      PPC: Create and use CONFIG_HIGH_BATS · 31d82672
      Becky Bruce authored
      
      
      Change all code that conditionally operates on high bat
      registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
      instead of the myriad ways this is done now.  Define the option
      for every config for which high bats are supported (and
      enabled by early boot, on parts where they're not always
      enabled)
      Signed-off-by: default avatarBecky Bruce <becky.bruce@freescale.com>
      31d82672
  7. 24 Apr, 2008 1 commit
  8. 28 Mar, 2008 1 commit
  9. 14 Feb, 2008 1 commit
  10. 11 Jan, 2008 1 commit
  11. 22 Jun, 2007 1 commit
  12. 02 Mar, 2007 1 commit
  13. 04 Nov, 2006 3 commits
    • Timur Tabi's avatar
      mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR · d239d74b
      Timur Tabi authored
      
      
      Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
      tree matches the other 8xxx trees.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      d239d74b
    • Dave Liu's avatar
      mpc83xx: Fix the incorrect dcbz operation · 90f30a71
      Dave Liu authored
      
      
      The 834x rev1.x silicon has one CPU5 errata.
      
      The issue is when the data cache locked with
      HID0[DLOCK], the dcbz instruction looks like no-op inst.
      
      The right behavior of the data cache is when the data cache
      Locked with HID0[DLOCK], the dcbz instruction allocates
      new tags in cache.
      
      The 834x rev3.0 and later and 8360 have not this bug inside.
      
      So, when 834x rev3.0/8360 are working with ECC, the dcbz
      instruction will corrupt the stack in cache, the processor will
      checkstop reset.
      
      However, the 834x rev1.x can work with ECC with these code,
      because the sillicon has this cache bug. The dcbz will not
      corrupt the stack in cache.
      Really, it is the fault code running on fault sillicon.
      
      This patch fix the incorrect dcbz operation. Instead of
      CPU FP writing to initialise the ECC.
      
      CHANGELOG:
      * Fix the incorrect dcbz operation instead of CPU FP
      writing to initialise the ECC memory. Otherwise, it
      will corrupt the stack in cache, The processor will checkstop
      reset.
      Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
      90f30a71
    • Timur Tabi's avatar
      mpc83xx: Add support for variable flash memory sizes on 83xx systems · 31068b7c
      Timur Tabi authored
      
      
      CHANGELOG:
      
      * On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
         window registers, instead of using a hard-coded value of 8MB.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      31068b7c
  14. 14 Mar, 2006 2 commits
  15. 10 Feb, 2006 1 commit
  16. 11 Jan, 2006 1 commit
  17. 01 Aug, 2005 1 commit
  18. 28 Jul, 2005 1 commit