1. 03 Aug, 2015 1 commit
    • York Sun's avatar
      drivers/ddr/fsl: Adjust bstopre value · 56848428
      York Sun authored
      
      
      By default the bstopre value has been set to 0x100, used to be 1/4
      value of refint. Modern DDR has increased the refresh time. Adjust
      to 1/4 of refresh interval dynamically. Individual board can still
      override this value in board ddr file, or to use auto-precharge.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      56848428
  2. 23 Apr, 2015 1 commit
  3. 24 Feb, 2015 1 commit
  4. 25 Sep, 2014 2 commits
  5. 23 Apr, 2014 2 commits
  6. 21 Feb, 2014 1 commit
  7. 25 Nov, 2013 1 commit
  8. 16 Oct, 2013 1 commit
  9. 09 Aug, 2013 1 commit
  10. 24 Jul, 2013 1 commit
  11. 22 Oct, 2012 2 commits
    • York Sun's avatar
      powerpc/mpc8xxx: Add auto select bank interleaving mode · 89b78095
      York Sun authored
      
      
      Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
      cs0_cs1 interleaving, or non-interleaving if not available.
      
      Fix the message of interleaving disabled if controller interleaving
      is enabled but DIMMs don't support it.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      89b78095
    • York Sun's avatar
      powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation · 123922b1
      York Sun authored
      
      
      Fix handling quad-rank DIMMs in a system with two DIMM slots and first
      slot supports both dual-rank DIMM and quad-rank DIMM.
      
      For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
      registers need to be enabled to maintain proper ODT operation. The
      inactive CS should have bnds registers cleared.
      
      Fix the turnaround timing for systems with all chip-selects enabled. This
      wasn't an issue before because DDR was running lower than 1600MT/s with
      this interleaving mode.
      
      Fix DDR address calculation. It wasn't an issue until we have multiple
      controllers with each more than 4GB and interleaving is disabled.
      
      It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
      when debugging DDR and first DDR controller is disabled. With the fix,
      the first enabled controller information will be displayed.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      123922b1
  12. 23 Aug, 2012 2 commits
  13. 11 Nov, 2011 1 commit
  14. 30 Sep, 2011 2 commits
  15. 11 Jul, 2011 3 commits
  16. 20 Jan, 2011 3 commits
    • York Sun's avatar
      mpc85xx: Enable unique mode registers and dynamic ODT for DDR3 · e1fd16b6
      York Sun authored
      
      
      Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version
      (major, minor, errata) to determine if unique mode registers are available.
      If true, always use unique mode registers. Dynamic ODT is enabled if needed.
      The table is documented in doc/README.fsl-ddr. This function may also need
      to be extend for future other platforms if such a feature exists.
      
      Enable address parity and RCW by default for RDIMMs.
      
      Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for
      quad-rank RDIMMs.
      
      Use a formula to calculate rodt_on for timing_cfg_5.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      e1fd16b6
    • York Sun's avatar
      mpc8xxx: Enable ECC on/off control in hwconfig · 47df8f03
      York Sun authored
      
      
      Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file,
      ECC can be turned on/off by this switch. If this switch is omitted, it is ON by
      default.
      
      Updated hwconfig calls to use local buffer.
      
      Syntax is
      hwconfig=fsl_ddr:ecc=on
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      47df8f03
    • Kumar Gala's avatar
      powerpc/8xxx: Add hwconfig APIs to address early parsing used by DDR init · dd50af25
      Kumar Gala authored
      
      
      There are several users of the hwconfig APIs (8xxx DDR) before we have
      the environment properly setup.  This causes issues because of the
      numerous ways the environment might be accessed because of the
      non-volatile memory it might be stored in.  Additionally the access
      might be so early that memory isn't even properly setup for us.
      
      Towards resolving these issues we provide versions of all the hwconfig
      APIs that can be passed in a buffer to parse and leave it to the caller
      to determine how to allocate and populate the buffer.
      
      We use the _f naming convention for these new APIs even though they are
      perfectly useable after relocation and the environment being ready.
      
      We also now warn if the non-f APIs are called before the environment is
      ready to allow users to address the issues.
      
      Finally, we convert the 8xxx DDR code to utilize the new APIs to
      hopefully address the issue once and for all.  We have the 8xxx DDR code
      create a buffer on the stack and populate it via getenv_f().
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      Acked-by: default avatarWolfgang Denk <wd@denx.de>
      dd50af25
  17. 14 Jan, 2011 1 commit
  18. 26 Jul, 2010 5 commits
  19. 21 Apr, 2010 1 commit
  20. 13 Apr, 2010 1 commit
  21. 07 Apr, 2010 1 commit
  22. 05 Jan, 2010 1 commit
  23. 12 Nov, 2009 1 commit
  24. 30 Mar, 2009 1 commit
  25. 17 Feb, 2009 1 commit
  26. 23 Jan, 2009 1 commit
  27. 04 Dec, 2008 1 commit