1. 22 Oct, 2012 1 commit
    • York Sun's avatar
      powerpc/mpc8xxx: Update DDR registers · 57495e4e
      York Sun authored
      DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
      set for speed lower than 1250MT/s.
      
      CDR1 and CDR2 are control driver registers. ODT termination valueis for
      IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
      	000 -> Termsel off
      	001 -> 120 Ohm
      	010 -> 180 Ohm
      	011 -> 75 Ohm
      	100 -> 110 Ohm
      	101 -> 60 Ohm
      	110 -> 70 Ohm
      	111 -> 47 Ohm
      
      Add two write leveling registers. Each QDS now has its own write leveling
      start value. In case of zero value, the value of QDS0 will be used. These
      values are board-specific and are set in board files.
      
      Extend DDR register timing_cfg_1 to have 4 bits for each field.
      
      DDR control driver registers and write leveling registers are added to
      interactive debugging for easy access.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      57495e4e
  2. 23 Aug, 2012 2 commits
  3. 08 Aug, 2012 1 commit
  4. 29 Nov, 2011 1 commit
    • York Sun's avatar
      powerpc/85xx: Add workaround for erratum A-003474 · 4108508a
      York Sun authored
      Erratum A-003474: Internal DDR calibration circuit is not supported
      
      Impact:
      Experience shows no significant benefit to device operation with
      auto-calibration enabled versus it disabled. To ensure consistent timing
      results, Freescale recommends this feature be disabled in future customer
      products. There should be no impact to parts that are already operating
      in the field.
      
      Workaround:
      Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
      1. Write a value of 0x0000_0015 to the register at offset
      	CCSRBAR + DDR OFFSET + 0xf30
      2. Write a value of 0x2400_0000 to the register at offset
      	CCSRBAR + DDR OFFSET + 0xf54
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      4108508a
  5. 24 Mar, 2011 1 commit
  6. 03 Feb, 2011 3 commits
  7. 20 Jan, 2011 3 commits
  8. 26 Jul, 2010 1 commit
  9. 21 Apr, 2010 1 commit
  10. 13 Apr, 2010 1 commit
  11. 03 Oct, 2009 1 commit
  12. 08 Sep, 2009 1 commit
  13. 30 Mar, 2009 1 commit
  14. 09 Mar, 2009 1 commit
  15. 17 Feb, 2009 1 commit
  16. 24 Oct, 2008 1 commit
    • Dave Liu's avatar
      85xx: Fix the incorrect register used for DDR erratum1 · ae5f943b
      Dave Liu authored
      The 8572 DDR erratum1:
      DDR controller may enter an illegal state when operating
      in 32-bit bus mode with 4-beat bursts.
      
      Description:
      When operating with a 32-bit bus, it is recommended that
      DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
      This forces the DDR controller to use 4-beat bursts when
      communicating to the DRAMs. However, an issue exists that
      could lead to data corruption when the DDR controller is
      in 32-bit bus mode while using 4-beat bursts.
      
      Projected Impact:
      If the DDR controller is operating in 32-bit bus mode with
      4-beat bursts, then the controller may enter into a bad state.
      All subsequent reads from memory is corrupted.
      Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
      Therefore, this erratum does not affect DDR3 mode.
      
      Work Arounds:
      To work around this issue, software must set DEBUG_1[31] in
      DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
      and CCSRBAR offset + 0x6f00 for DDR_2).
      
      Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
      as condition, but it should be DDR_SDRAM_CFG register.
      Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
      ae5f943b
  17. 18 Oct, 2008 1 commit
  18. 27 Aug, 2008 2 commits