1. 30 Jan, 2013 3 commits
  2. 22 Oct, 2012 1 commit
  3. 23 Aug, 2012 1 commit
  4. 27 Mar, 2012 1 commit
  5. 09 Oct, 2011 1 commit
    • York Sun's avatar
      powerpc/8xxx: Add support for interactive DDR programming interface · 6f5e1dc5
      York Sun authored
      Interactive DDR debugging provides a user interface to view and modify SPD,
      DIMM parameters, board options and DDR controller registers before DDR is
      initialized. With this feature, developers can fine-tune DDR for board
      bringup and other debugging without frequently having to reprogram the flash.
      To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
      file and set an environment variable to activate it. Syntax:
      setenv ddr_interactive on
      After reset, U-boot prompts before initializing DDR controllers
      FSL DDR>
      The available commands are
      print      print SPD and intermediate computed data
      reset      reboot machine
      recompute  reload SPD and options to default and recompute regs
      edit       modify spd, parameter, or option
      compute    recompute registers from current next_step to end
      next_step  shows current next_step
      help       this message
      go         program the memory controller and continue with u-boot
      The first command should be "compute", which reads data from DIMM SPDs and
      board options, performs the calculation then stops before setting DDR
      controller. A user can use "print" and "edit" commands to view and modify
      anything. "Go" picks up from current step with any modification and
      compltes the calculation then enables the DDR controller to continue u-boot.
      "Recompute" does it over from fresh reading.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  6. 30 Sep, 2011 1 commit
  7. 02 Feb, 2011 1 commit
  8. 20 Jan, 2011 2 commits
  9. 20 Oct, 2010 1 commit
    • York Sun's avatar
      Add memory test feature for mpc85xx POST. · ebbe11dd
      York Sun authored
      The memory test is performed after DDR initialization when U-boot stills runs
      in flash and cache. On recent mpc85xx platforms, the total memory can be more
      than 2GB. To cover whole memory, it needs be mapped 2GB at a time using a
      sliding TLB window. After the testing, DDR is remapped with up to 2GB memory
      from the lowest address as normal.
      If memory test fails, DDR DIMM SPD and DDR controller registers are dumped for
      further debugging.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  10. 26 Jul, 2010 3 commits
  11. 18 Oct, 2008 1 commit