1. 03 Sep, 2008 2 commits
    • Andy Fleming's avatar
      Add pixis_set_sgmii command · 5a8a163a
      Andy Fleming authored
      The 8544DS and 8572DS platforms support an optional SGMII riser card to
      expose ethernet over an SGMII interface.  Once the card is in, it is also
      necessary to configure the board such that it uses the card, rather than
      the on-board ethernet ports.  This can either be done by flipping dip switches
      on the motherboard, or by modifying registers in the pixis.  Either way
      requires a reboot.
      This adds a command to allow users to choose which ports are routed through
      the SGMII card, and which through the onboard ports.  It also allows users
      to revert to the current switch settings.
      This code does not work on the 8572, as the PIXIS is different.
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      Signed-off-by: default avatarBen Warren <biggerbadderben@gmail.com>
    • Andy Fleming's avatar
      Add support for Freescale SGMII Riser Card · 652f7c2e
      Andy Fleming authored
      The 8544DS and 8572DS systems have an optional SGMII riser card which
      exposes new ethernet ports which are connected to the eTSECs via an
      SGMII interface.  The SGMII PHYs for this board are offset from the standard
      PHY addresses, so this code modifies the passed in tsec_info structure to
      use the SGMII PHYs on the card, instead.
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      Signed-off-by: default avatarBen Warren <biggerbadderben@gmail.com>
  2. 27 Aug, 2008 1 commit
  3. 12 Aug, 2008 1 commit
  4. 15 Jul, 2008 3 commits
  5. 14 Jul, 2008 1 commit
    • Andy Fleming's avatar
      Remove LBC_CACHE_BASE from 8544 DS · ab5cda9f
      Andy Fleming authored
      The 8544 DS doesn't have any cacheable Local Bus memories set up.  By mapping
      space for some anyway, we were allowing speculative loads into unmapped space,
      which would cause an exception (annoying, even if ultimately harmless).
      Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
  6. 11 Jun, 2008 3 commits
  7. 25 Apr, 2008 1 commit
  8. 26 Mar, 2008 1 commit
  9. 17 Jan, 2008 3 commits
  10. 09 Jan, 2008 1 commit
  11. 12 Dec, 2007 4 commits
  12. 16 Nov, 2007 1 commit
  13. 07 Nov, 2007 1 commit
  14. 04 Sep, 2007 1 commit
    • Kumar Gala's avatar
      Fix ULI RTC support on MPC8544 DS · 56a92705
      Kumar Gala authored
      The RTC on the M1575 ULI chipset requires a dummy read before
      we are able to talk to the RTC.  We accomplish this by adding a
      second memory region to the PHB the ULI is on and read from it.
      The second region is added to maintain compatiabilty with Linux's
      view of the PCI memory map.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  15. 29 Aug, 2007 1 commit
    • Kim Phillips's avatar
      support board vendor-common makefiles · 7608d75f
      Kim Phillips authored
      if a board/$(VENDOR)/common/Makefile exists, build it.
      also add the first such case, board/freescale/common/Makefile, to
      handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
      dictated by board configuration.
      thusly get rid of alternate build dir errors such as:
      FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
      by putting the common/ mkdir command in its proper place (the common
      Makefile). Common bits from existing individual board Makefiles have
      been removed.
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
  16. 28 Aug, 2007 1 commit
  17. 16 Aug, 2007 3 commits
    • Kumar Gala's avatar
      Update MPC8544 DS PCI memory map · d64ee908
      Kumar Gala authored
      The PCIe bus that the ULI M1575 is connected to has no possible way of
      needing more than the fixed amount of IO & Memory space needed by the ULI.
      So make it use far less IO & memory space and have it use the shared LAW.  This
      free's up a LAW for PCIe1 IO space.  Also reduce the amount of IO space needed
      by each bus.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Kumar Gala's avatar
      Fix up some fdt issues on 8544DS · ea5877e3
      Kumar Gala authored
      It looks like we had a merge issue that duplicated a bit of code
      in ft_board_setup.  Also, we need to set CONFIG_HAS_ETH0 to get
      the MAC address properly set in the device tree on boot for TSEC1
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Andy Fleming's avatar
      Define tsec flag values in config files · 3a79013e
      Andy Fleming authored
      The tsec_info structure and array has a "flags" field for each
      ethernet controller.  This field is the only reason there are
      settings.  Switch to defining TSECn_FLAGS for each controller
      in the config header, and we can greatly simplify the array, and
      also simplify the addition of future boards.
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
  18. 14 Aug, 2007 1 commit
    • Ed Swarthout's avatar
      8544ds PCIE support · 837f1ba0
      Ed Swarthout authored
      PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
      Enable LBC and ECM errors and clear error registers.
      Add tftpflash env var to get uboot from tftp server and flash it.
      Add pci/pcie convenience env vars to display register space:
        "run pcie3regs" to see all pcie3 ccsr registers
        "run pcie3cfg" to see all cfg registers
      Whitespace cleanup and MPC8544DS.h
      Signed-off-by: default avatarEd Swarthout <Ed.Swarthout@freescale.com>
      Acked-by: default avatarAndy Fleming <afleming@freescale.com>
  19. 10 Jul, 2007 1 commit
  20. 05 Jul, 2007 1 commit
  21. 16 May, 2007 1 commit
  22. 24 Apr, 2007 1 commit