1. 26 Mar, 2008 4 commits
    • Michael Barkowski's avatar
      mpc8323erdb: Improve the system performance · 5bbeea86
      Michael Barkowski authored
      
      
      The following changes are based on kernel UCC ethernet performance:
      
      1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
      2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
          switch to enable this setting.
      
      The following changes are based on the App Note AN3369 and
      verified to improve memory latency using LMbench:
      
      3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
      4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
          previously.
      5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
          Twr=15ns, and this was already the setting in DDR_MODE)
      6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
          Trp=15ns)
      7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
          Tras=40ns)
      8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
          Trcd=15ns)
      9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
          Trfc=75ns)
      10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
          on Tfaw=50ns)
      11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
          on CL=3 and WL=2).
      Signed-off-by: default avatarMichael Barkowski <michael.barkowski@freescale.com>
      Acked-by: default avatarKim Phillips <kim.phillips@freescale.com>
      5bbeea86
    • Michael Barkowski's avatar
      mpc8323erdb: use readable DDR config macros · fc549c87
      Michael Barkowski authored
      
      
      Use available shift/mask macros to define DDR configuration.
      Signed-off-by: default avatarMichael Barkowski <michael.barkowski@freescale.com>
      Acked-by: default avatarKim Phillips <kim.phillips@freescale.com>
      fc549c87
    • Timur Tabi's avatar
      83xx: Add Vitesse VSC7385 firmware uploading · 89c7784e
      Timur Tabi authored
      
      
      Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
      the Vitesse VSC7385 firmware.  Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
      Cleaned up the board header files to make selecting the VSC7385 easier to
      control.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
      89c7784e
    • Timur Tabi's avatar
      NET: Add Vitesse VSC7385 firmware uploading · b55d98c6
      Timur Tabi authored
      
      
      The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
      and other boards.  A small firwmare must be uploaded to its on-board memory
      before it can be enabled.  This patch adds the code which uploads firmware
      (but not the firmware itself).
      
      Previously, this feature was provided by a U-Boot application that was
      made available only on Freescale BSPs.  The VSC7385 firmware must still
      be obtained separately, but at least there is no longer a need for a separate
      application.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Acked-by: default avatarBen Warren <biggerbadderben@gmail.com>
      b55d98c6
  2. 25 Mar, 2008 35 commits
  3. 24 Mar, 2008 1 commit
    • Yuri Tikhonov's avatar
      lwmon5 SYSMON POST: fix backlight control · 0d48926c
      Yuri Tikhonov authored
      
      
      If the LWMON5 config has SYSMON POST among CONFIG_POSTs which may be
      run on the board, then the SYSMON POST controls the display backlight
      (doesn't switch backlight ON if POST FAILED, and does switch the
      backlight ON if PASSED).
      
      If not, then the video driver controls the display backlight (just
      switch ON the backlight upon initialization).
      Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
      0d48926c