- 07 Apr, 2008 4 commits
-
-
-
git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk authored
Conflicts: lib_ppc/board.c Signed-off-by:Wolfgang Denk <wd@denx.de>
-
-
-
- 03 Apr, 2008 1 commit
-
-
Stefan Roese authored
This patch fixes a problem with the RGMII setup of the 460GT. The 460GT has 2 RGMII instances and we need to configure the 2nd RGMII instance for the EMAC2+3 channels. Signed-off-by:
-
- 02 Apr, 2008 1 commit
-
-
Stefan Roese authored
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch correctly configures the SATA/PCIe PHY for SATA usage when this jumper is installed. Signed-off-by:
-
- 31 Mar, 2008 5 commits
-
-
Larry Johnson authored
Signed-off-by: -
Stefan Roese authored
Signed-off-by: -
Matthias Fuchs authored
Signed-off-by: -
Matthias Fuchs authored
Add support for the ptm1la, ptm1ms, ptm2la and ptm2ms environment variables. Cleanup pci_target_init. Signed-off-by: -
Matthias Fuchs authored
Signed-off-by:
-
- 29 Mar, 2008 1 commit
-
-
Daniel Hellstrom authored
SPARC has implemented __raw_readq, it reads 64-bit from any 32-bit address. SPARC CPUs implement flash_read64 which calls __raw_readq. For current SPARC architectures (LEON2 and LEON3) each read from the FLASH must lead to a cache miss. This is because FLASH can not be set non-cacheable since program code resides there, and alternatively disabling cache is poor from performance view, or doing a cache flush between each read is even poorer. Forcing a cache miss on a SPARC is done by a special instruction "lda" - load alternative space, the alternative space number (ASI) is processor implementation spcific and can be found by including <asm/processor.h>. Signed-off-by:
-
- 28 Mar, 2008 27 commits
-
-
Joakim Tjernlund authored
Remove a few absolute references to CFG_MONITOR_BASE for ppc/mpc83xx and use GOT relative reference. Signed-off-by:
-
Michael Barkowski authored
This patch fixes eeprom page size so that you can now write more than 64 bytes at a time. It also makes the board take MAC addresses, if found, from EEPROM. User should place up to 4 addresses at offset 0x7f00, for eth{,1,2,3}addr. Any unused addresses should be zero. This group of four six-byte values should have it's CRC at the end. crc32 and eeprom commands can be used to accomplish this. If CRC fails, MAC addresses come from the environment. If CRC succeeds, the environment is overwritten at startup. Signed-off-by: -
Michael Barkowski authored
Commit 55774b51 broke the onboard USB controller on the PCI bus in Linux on the MPC8323ERDB. This fixes it by defining CONFIG_PCI_SKIP_HOST_BRIDGE in the board's config file. Signed-off-by:
-
Kim Phillips authored
in the spirit of commit 1ced1216 , 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing and processor ID display. Add REVID_{MAJ,MIN}OR macros to make REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR convenience macros. Signed-off-by:
-
Kim Phillips authored
Signed-off-by: -
Kim Phillips authored
delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: -
Kim Phillips authored
Signed-off-by: -
Dave Liu authored
Enable the first two SATA interfaces on MPC837xEMDS board, The two SATA ports are on LYNX1. (SATA0/1 on J4/5) Signed-off-by:
-
Dave Liu authored
This patch is stolen from Anton Vorontsov's patch for mpc837xerdb boards. The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb. 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE 8379E: LYNX1- 2 SATA LYNX2- 2 SATA Signed-off-by:
-
Stefan Roese authored
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: -
Tor Krill authored
Add entry for 512Kx16 AMD flash to jedec_table. Read out 16bit device id if chipwidth is 16bit. Fixed coding style after Stefans feedback Signed-off-by: -
Stefan Roese authored
Signed-off-by: -
Nobuhiro Iwamatsu authored
Signed-off-by: -
Mark Jonas authored
Signed-off-by:
-
Nobuhiro Iwamatsu authored
Signed-off-by: -
Nobuhiro Iwamatsu authored
Update MAINTAINER entry for R7780MP. And fix maintainer's name. Signed-off-by: -
Nobuhiro Iwamatsu authored
R2D plus is SH reference board used with SH7751R. This board has 266Mhz CPU, 64MB SDRAM, Cardbus, CF interface, one PCI bus, VGA, and two Ethernet controller. Signed-off-by: -
Nobuhiro Iwamatsu authored
Add support SH4 cache control and flash_cache function Signed-off-by: -
Nobuhiro Iwamatsu authored
Signed-off-by: -
Nobuhiro Iwamatsu authored
Signed-off-by: -
Nobuhiro Iwamatsu authored
Signed-off-by: -
Mark Jonas authored
Signed-off-by:
-
Nobuhiro Iwamatsu authored
Receive FIFO level register is different in SH4A. Because register is different, cannot occasionally receive data. Signed-off-by: -
Yusuke Goda authored
Renesas Solutions R7780MP is a reference board on SH7780. This board has serial, 10/100 base Ethernet deivice, CF slot and VGA devices. This board can set extension board. Extension board has 10/100/1000 base Ethernet device, PCI slot, S-ATA, iDVR slot. Signed-off-by:
-
Yusuke Goda authored
This patch add support PCI of SuperH base code and SH7780 specific code. Signed-off-by:
-
Yusuke Goda authored
SH7780 is CPU of Renesas Technology. This CPU has - CPU clock 400MHz - PCI support - DDR-SDRAM controller - etc ... Signed-off-by:
-
goda.yusuke authored
Migo-R is a board based on SH7722 and has may devices. In this patch, supported SCIF, NOR flash and Ethernet. Signed-off-by:
-
- 27 Mar, 2008 1 commit
-
-
Bartlomiej Sieka authored
Revert commit 87c8431f and fix build breakage so that the build continues to work on FC systems. Signed-off-by:
-