- 23 Aug, 2012 21 commits
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Timur Tabi authored
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and so on. This is pointless, so remove it. Also move the lane_to_slot[] array to the top of the file so that it can be used by other functions. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Timur Tabi authored
We have a dedicated function for setting the node status now, so use it. Also improve a comment and fix the type of the phandle variable. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Timur Tabi authored
In order to figure out which SerDes lane a given Fman port is connected to, we need a function that maps the fm_port namespace to the srds_prtcl namespace. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Timur Tabi authored
Function fm_info_get_phy_address() returns the PHY address for a given Fman port. This is handy when the MDIO code needs to fixup the Ethernet nodes in the device tree to point to PHY nodes for a specific PHY address. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Timur Tabi authored
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Paul Gortmaker authored
Using the raw value of 0x80000000 directly in the code can lead to "count the zeros" bugs like that fixed in commit 718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC") Change all existing raw values to use the symbolic value of LCRR_DBYP instead. Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Matthew McClintock authored
This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync Done with: sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` Signed-off-by:
Matthew McClintock <msm@freescale.com> Acked-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Matthew McClintock authored
We have a requirement to wait a period of time before enabling the DDR controller Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Matthew McClintock authored
Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time. Looked at reusing the u-boot udelay functions but it pulls in a lot of code and would require quite a bit of work to keep us within the very small space constrains we currently have Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Matthew McClintock authored
We were not comparing the SVRs properly previously. This comparison will properly shift the SVR and mask off the E bit This fixes the boot output to show the correct DDR bus width: 512 MiB (DDR3, 16-bit, CL=5, ECC off) instead of 512 MiB (DDR3, 32-bit, CL=5, ECC off) Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Matthew McClintock authored
There was an extra 0 in front of the value we were using to mask, remove it to improve the code. Also fix the value written to ddr_sdram_cfg to set the bus width properly to 16 bits Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Matthew McClintock authored
Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by:
Matthew McClintock <msm@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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York Sun authored
P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Shaohui Xie authored
Provides a tool to build boot Image for PBL(Pre boot loader) which is used on Freescale CoreNet SoCs, PBL can be used to load some instructions and/or data for pre-initialization. The default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by:
Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Liu Gang authored
When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Liu Gang authored
For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Liu Gang authored
Added descriptions about boot from PCIE in the files README and doc/README.srio-pcie-boot-corenet, and changed the name of the doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Liu Gang authored
When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Liu Gang authored
Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Liu Gang authored
Update some descriptions due to the implementation changes: For master: Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. For slave: 1. When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. 2. All slave's cores should be in hold off. Signed-off-by:
Liu Gang <Gang.Liu@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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York Sun authored
This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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- 22 Aug, 2012 3 commits
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Scott Wood authored
This is needed to make room for a bugfix on p1_p2_rdb_pc. A sync is used before the final write to LSOR that initiates the transaction, to ensure all the other set up has been completed. Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Joakim Tjernlund authored
The code first aligns the SP to 16 then subtract 8, making it 8 bytes aligned. Furthermore the initial stack frame not quite correct either. Signed-off-by:
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Joakim Tjernlund authored
PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by:
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
Andy Fleming <afleming@freescale.com>
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- 17 Aug, 2012 1 commit
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Scott Wood authored
Commit 8b5a0264 ("Makefile: cosmetic: optimize usage of LIBS-y") broke the build of boards that have a board vendor "common" directory, by introducing a space between "LIBS-" and "y". Signed-off-by:
Scott Wood <scottwood@freescale.com> Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by:
Kim Phillips <kim.phillips@freescale.com>
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- 13 Aug, 2012 2 commits
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Holger Brunck authored
commit 54652991 Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips fixes a problem for Numonyx P33/P30 flashes for 256-Mbit, but this leads to problems for smaller versions of this chip e.g. the 32Mbit version with deviceid 0x16 on mgcoge. So move the code for this work around to an own function and check previously manufacturer id and device id to not break other flashes which don't need this work around. Signed-off-by:
Holger Brunck <holger.brunck@keymile.com> Signed-off-by:
Heiko Schocher <hs@denx.de> cc: Stefan Roese <sr@denx.de> cc: Philippe De Muyter <phdm@macqel.be> cc: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by:
Stefan Roese <sr@denx.de>
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Anatolij Gustschin authored
Erasing flash sectors protected with persistent protection bit (PPB) mechanism on Spansion flash chips doesn't work. Add sector protection status checking and sector lock and unlock commands to fix this. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by:
Stefan Roese <sr@denx.de>
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- 10 Aug, 2012 9 commits
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Horst Kronstorfer authored
Add '-ansi' to DTS_CPPFLAGS to avoid unwanted expansion of dts content that matches some predefined macros. Example: A number of PowerPC related *.dts files in the kernel define a property named 'linux,network-index' which (w/o '-ansi') is expanded to '1,network-index' by the preprocessor because of '#define linux 1.' Signed-off-by:
Horst Kronstorfer <hkronsto@frequentis.com>
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Kenth Eriksson authored
Support for DS1388 is added by extending the DS1337 driver. DS1388 is similar to DS1337. The time registers are offset by 1 (due to support for hundreds of seconds), and there is no century bit. The configuration and trickle charge registers are also different. Tested on hardware with Freescale P2010 and DS1388. Signed-off-by:
Kenth Eriksson <kenth.eriksson@transmode.com>
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Horst Kronstorfer authored
Make sure that $(LDSCRIPT) is not empty before calling process_lds with 'cat $(LDSCRIPT)' else cat will block waiting for input from stdin. Signed-off-by:
Horst Kronstorfer <hkronsto@frequentis.com>
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Daniel Schwierzeck authored
Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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Daniel Schwierzeck authored
Synchronize with ALL-y handling and code in spl/Makefile. Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by:
Mike Frysinger <vapier@gentoo.org>
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Daniel Schwierzeck authored
The top Makefile and the SPL Makefile have lines like those: ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) LIBS += $(CPUDIR)/omap-common/libomap-common.o endif ifeq ($(SOC),mx5) LIBS += $(CPUDIR)/imx-common/libimx-common.o endif This should be done in the arch/CPU/SoC specific sub-makefiles to keep the top Makefiles clean. This patch also allows adding of new arch/CPU/SoC specific libraries in the future without touching the top Makefiles. Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Fixes the build-time warning: board.c: At top level: board.c:106: warning: 'pmu_init' defined but not used This makes the ifdef logic at the call site match the logic at the function definition. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Fixes the build-time warning: board.c: In function 'board_init_r': board.c:304: warning: unused variable 's' Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Nothing is using this, so punt it from the gd. Seems to just be a copy & paste wart from the initial port. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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- 09 Aug, 2012 4 commits
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Jorgen Lundman authored
U-Boot port is based on sources forked from GRUB-0.97 by Sun in 2004, which can be found here: http://src.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/grub/grub-0.97/stage2/zfs-include/zfs.h Released by Sun for GRUB under the license: * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. GRUB official releases include ZFS in version: ftp://alpha.gnu.org/gnu/grub/grub-1.99~rc1.tar.gz And patched against GRUB Bazaar repository for ashift fixes (4KB HDDs) more conveniently found at github: https://github.com/pendor/grub-zfs/commit/e7b6ef3ac3b9685ac4c394c897b1d4221b7381f1Signed-off-by:
Jorgen Lundman <lundman@lundman.net>
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Charles Manning authored
This patch updates the yaffs2 in u-boot to correspond to git://www.aleph1.co.uk/yaffs2 commit id 9ee5d0643e559568dbe62215f76e0a7bd5a63d93 Signed-off-by:
Charles Manning <cdhmanning@gmail.com>
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Julius Baxter authored
When reset code is in flash, the jump instructions emitted by the compiler are relative instead of absolute jumps. A fix to the reset code to make correct jumps to the beginning of code relocated to RAM have also been added. Signed-off-by:
Julius Baxter <juliusbaxter@gmail.com>
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Jens Scharsig authored
* rename board directory to eb_cpu5282 * rename EB+MCF-EV123_.*config to eb_cpu5282_.*config * add Maintainer for EB+CPU5282 board * rename prompt Signed-off-by:
Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
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