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  1. 23 Aug, 2012 7 commits
    • Timur Tabi's avatar
      powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver · 61fc52b6
      Timur Tabi authored 
      enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on.  This is pointless, so remove it.  Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.
Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      61fc52b6
    • Timur Tabi's avatar
      powerpc/85xx: introduce function serdes_device_from_fm_port() · 45b092d3
      Timur Tabi authored 
      In order to figure out which SerDes lane a given Fman port is connected
to, we need a function that maps the fm_port namespace to the srds_prtcl
namespace.
Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      45b092d3
    • Paul Gortmaker's avatar
      mpc85xx: use LCRR_DBYP define instead of raw constant · a2af6a7a
      Paul Gortmaker authored 
      Using the raw value of 0x80000000 directly in the code can
lead to "count the zeros" bugs like that fixed in commit
718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC")

Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.

Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      a2af6a7a
    • Matthew McClintock's avatar
      p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit) · c8f9802a
      Matthew McClintock authored 
      There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.

Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bits
Signed-off-by: default avatarMatthew McClintock <msm@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      c8f9802a
    • Shaohui Xie's avatar
      powerpc/CoreNet: add tool to support pbl image build. · 5d898a00
      Shaohui Xie authored 
      Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.
Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      5d898a00
    • Liu Gang's avatar
      powerpc/corenet_ds: Slave module for boot from PCIE · 461632bd
      Liu Gang authored 
      When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE interface, so it can not modify the ENV parameters stored
	  in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE interface by RCW.
	3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
	1. Updated the README.srio-boot-corenet to add descriptions about
	   boot from PCIE, and change the name to
	   README.srio-pcie-boot-corenet.
	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
	   from PCIE.
	3. Updated other macros and documents if needed to add information
	   about boot from PCIE.
Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      461632bd
    • Liu Gang's avatar
      powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro · 81fa73ba
      Liu Gang authored 
      When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.
Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      81fa73ba
  3. 09 Aug, 2012 1 commit
  5. 08 Aug, 2012 4 commits
  7. 31 Jul, 2012 5 commits
  9. 29 Jul, 2012 1 commit
  11. 22 Jul, 2012 3 commits
  13. 20 Jul, 2012 1 commit
  15. 11 Jul, 2012 2 commits
  17. 10 Jul, 2012 2 commits
  19. 09 Jul, 2012 12 commits
  21. 07 Jul, 2012 2 commits