1. 01 Nov, 2013 4 commits
  2. 31 Oct, 2013 9 commits
  3. 24 Oct, 2013 5 commits
  4. 22 Oct, 2013 1 commit
  5. 20 Oct, 2013 14 commits
  6. 16 Oct, 2013 7 commits
    • Prabhakar Kushwaha's avatar
      boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLD · 787964b8
      Prabhakar Kushwaha authored
      
      
       NAND,CPLD AMASK register is programmed for 64K size.
      
      so Update TLB & LAW size accordingly.
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      787964b8
    • Shengzhou Liu's avatar
      powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-pa · e512c50b
      Shengzhou Liu authored
      
      
      - Rename old P1010RDB board as P1010RDB-PA.
      - Add support for new P1010RDB-PB board.
      - Some optimization.
      
      For more details, see board/freescale/p1010rdb/README.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      [York Sun: fix conflicts in boards.cfg]
      Acked-by: default avatarYork Sun <yorksun@freescale.com>
      e512c50b
    • Shengzhou Liu's avatar
      board/p1010rdb: add pin mux and sdhc support in any boot · ad89da0c
      Shengzhou Liu authored
      
      
      Since pins multiplexing, SDHC shares signals with IFC, with this patch:
      To enable SDHC in case of NOR/NAND/SPI boot
         a) For temporary use case in runtime without reboot system
            run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
         b) For long-term use case
            set 'esdhc' in hwconfig and save it.
      To enable IFC in case of SD boot
         a) For temporary use case in runtime without reboot system
            run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
         b) For long-term use case
            set 'ifc' in hwconfig and save it.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      ad89da0c
    • Shengzhou Liu's avatar
      powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM · 5536aeb0
      Shengzhou Liu authored
      
      
      Some boards use System EEPROM with 128-bytes instead of 256-bytes.
      Since we regard 256-bytes EEPROM as standard EEPROM with default
      value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can
      redefine MAX_NUM_PORTS in board-specific file to override the
      default MAX_NUM_PORTS.
      
      This patch doesn't impact on previous existing boards.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      5536aeb0
    • Shengzhou Liu's avatar
      powerpc/p1010rdb: remove unused cpld_show · 41c686d9
      Shengzhou Liu authored
      
      
      Function cpld_show() was for debug and not called, so clean it.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      41c686d9
    • Prabhakar Kushwaha's avatar
      powerpc/t1040qds: Add T1040QDS board · 7d436078
      Prabhakar Kushwaha authored
      
      
      T1040QDS is a high-performance computing evaluation, development and
      test platform supporting the T1040 QorIQ Power Architecture™ processor.
      
       T1040QDS board Overview
       -----------------------
       - Four e5500 cores, each with a private 256 KB L2 cache
       - 256 KB shared L3 CoreNet platform cache (CPC)
       - Interconnect CoreNet platform
       - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
         support
       - Data Path Acceleration Architecture (DPAA) incorporating acceleration
       for the following functions:
          -  Packet parsing, classification, and distribution
          -  Queue management for scheduling, packet sequencing, and congestion
          	management
          -  Cryptography Acceleration
          - RegEx Pattern Matching Acceleration
          - IEEE Std 1588 support
          - Hardware buffer management for buffer allocation and deallocation
       - Ethernet interfaces
          - Integrated 8-port Gigabit Ethernet switch
          - Four 1 Gbps Ethernet controllers
       - SERDES Connections, 8 lanes supporting:
            — PCI Express: supporting Gen 1 and Gen 2;
            — SGMII
            — QSGMII
            — SATA 2.0
            — Aurora debug with dedicated connectors
       - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
         Interleaving
       -IFC/Local Bus
           - NAND flash: 8-bit, async, up to 2GB.
           - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
           - GASIC: Simple (minimal) target within Qixis FPGA
           - PromJET rapid memory download support
       - Ethernet
           - Two on-board RGMII 10/100/1G ethernet ports.
           - PHY #0 remains powered up during deep-sleep
       - QIXIS System Logic FPGA
       - Clocks
           - System and DDR clock (SYSCLK, “DDRCLK”)
           - SERDES clocks
       - Power Supplies
       - Video
           - DIU supports video at up to 1280x1024x32bpp
       - USB
           - Supports two USB 2.0 ports with integrated PHYs
           — Two type A ports with 5V@1.5A per port.
           — Second port can be converted to OTG mini-AB
       - SDHC
           - SDHC port connects directly to an adapter card slot, featuring:
           - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
           — Supporting eMMC memory devices
       - SPI
          -  On-board support of 3 different devices and sizes
       - Other IO
          - Two Serial ports
          - ProfiBus port
          - Four I2C ports
      Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
      Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
      [York Sun: fix conflict in boards.cfg]
      Acked-by-by: default avatarYork Sun <yorksun@freescale.com>
      7d436078
    • Priyanka Jain's avatar
      powerpc: Fix CamelCase warnings in DDR related code · 0dd38a35
      Priyanka Jain authored
      
      
      Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
      has various parameters with embedded acronyms capitalized that trigger the CamelCase
      warning in checkpatch.pl
      
      Convert those variable names to smallcase naming convention and modify all files
      which are using these structures with modified structures.
      Signed-off-by: default avatarPriyanka Jain <Priyanka.Jain@freescale.com>
      0dd38a35