1. 12 Feb, 2015 2 commits
  2. 10 Feb, 2015 3 commits
    • Nikita Kiryanov's avatar
      lcd: dt: extract simplefb support · 033167c4
      Nikita Kiryanov authored
      
      
      We now have api functions that can support compiling simplefb code as its own
      module. Since this code is not part of the display functionality, extract it
      to its own file.
      
      Raspberry Pi is updated to accommodate the changes.
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
      Acked-by: default avatarStephen Warren <swarren@wwwdotorg.org>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarBo Shen <voice.shen@atmel.com>
      Tested-by: default avatarJosh Wu <josh.wu@atmel.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Anatolij Gustschin <agust@denx.de>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      033167c4
    • Fabio Estevam's avatar
      mx53loco: Fix boot hang during reboot stress test · aee0013e
      Fabio Estevam authored
      
      
      Currently by running the following test:
      
      => setenv bootcmd reset
      => save
      => reset
      
      , we observe a hang after approximately 20-30 minutes of stress reboot test.
      
      Investigation of this issue revealed that when a single DDR chip select is used,
      the hang does not happen. It only happens when the two chip selects are active.
      
      MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":
      
      "The controller must keep the memory lines quiet (except for CK) for the ZQ
      calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
      for other ZQCL and 64 for ZQCS)."
      
      According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:
      
      "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
      Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"
      
      So make sure to activate one chip select at time (CS0 first and then CS1 later),
      so that the required JEDEC delay is respected for each chip select.
      
      With this change applied the board has gone through three days of reboot stress
      test without any hang.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Acked-by: default avatarStefano Babic <sbabic@denx.de>
      aee0013e
    • Ye.Li's avatar
      imx: mx6qsabreauto: Change to use common GPMI IO clock function · 5f22d88f
      Ye.Li authored
      
      
      Since a clock function setup_gpmi_io_clk is implemented for GPMI
      IO clock settings, change to use this common function in GPMI setup.
      Signed-off-by: default avatarYe.Li <B37916@freescale.com>
      Acked-by: default avatarStefano Babic <sbabic@denx.de>
      5f22d88f
  3. 09 Feb, 2015 2 commits
  4. 07 Feb, 2015 2 commits
  5. 06 Feb, 2015 7 commits
  6. 02 Feb, 2015 10 commits
  7. 30 Jan, 2015 7 commits
  8. 29 Jan, 2015 7 commits