1. 12 Feb, 2015 2 commits
  2. 07 Mar, 2014 1 commit
    • Stefan Roese's avatar
      ppc4xx: Remove 4xx NAND booting support · 345b77ba
      Stefan Roese authored
      
      
      As ppc4xx currently only supports the deprecated nand_spl infrastructure
      and nobody seems to have time / resources to port this over to the newer
      SPL infrastructure, lets remove NAND booting completely.
      
      This should not affect the "normal", non NAND-booting ppc4xx platforms
      that are currently supported.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Tirumala Marri <tmarri@apm.com>
      Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
      Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
      Cc: Tom Rini <trini@ti.com>
      Tested-by: default avatarMatthias Fuchs <matthias.fuchs@esd.eu>
      345b77ba
  3. 24 Jan, 2014 1 commit
  4. 24 Jul, 2013 1 commit
  5. 23 Jul, 2013 1 commit
  6. 07 Jun, 2013 1 commit
    • Gabor Juhos's avatar
      pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option · 842033e6
      Gabor Juhos authored
      
      
      The pci_indirect.c file is always compiled when
      CONFIG_PCI is defined although the indirect PCI
      bridge support is not needed by every board.
      
      Introduce a new CONFIG_PCI_INDIRECT_BRIDGE
      config option and only compile indirect PCI
      bridge support if this options is enabled.
      
      Also add the new option into the configuration
      files of the boards which needs that.
      
      Compile tested for powerpc, x86, arm and nds32.
      MAKEALL results:
      
      powerpc:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 641
        Boards with warnings but no errors: 2 ( ELPPC MPC8323ERDB )
        ----------------------------------------------------------
        Note: the warnings for ELPPC and MPC8323ERDB are present even
        without the actual patch.
      
      x86:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 1
        ----------------------------------------------------------
      
      arm:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 311
        ----------------------------------------------------------
      
      nds32:
        --------------------- SUMMARY ----------------------------
        Boards compiled: 3
        ----------------------------------------------------------
      
      Cc: Tom Rini <trini@ti.com>
      Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
      Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
      842033e6
  7. 26 Jan, 2012 1 commit
    • Scott Wood's avatar
      nand_spl: store ecc data on the stack · 25efd99d
      Scott Wood authored
      
      
      Adapt the following patch from spl to nand_spl:
      
        Author: Stefano Babic <sbabic@denx.de>
        Date:   Thu Dec 15 10:55:37 2011 +0100
      
            nand_spl_simple: store ecc data on the stack
      
            Currently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM
            which is likely to contain already loaded data.
            The patch saves the oob data and the ecc on the stack replacing
            the fixed address in RAM.
      Signed-off-by: default avatarStefano Babic <sbabic@denx.de>
            CC: Ilya Yanok <yanok@emcraft.com>
            CC: Scott Wood <scottwood@freescale.com>
            CC: Tom Rini <tom.rini@gmail.com>
            CC: Simon Schwarz <simonschwarzcor@googlemail.com>
            CC: Wolfgang Denk <wd@denx.de>
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      
      While nand_spl is on its way out, in favor of spl, there are still
      many boards using it, and conversions are gradual.  This allows us
      to get rid of CONFIG_SYS_NAND_ECCSTEPS and CONFIG_SYS_NAND_ECCTOTAL now,
      which would otherwise be likely to linger unreferenced after a conversion.
      
      It also eliminates a temporary error in the hawkboard_nand build, since
      the spl version of the patch removed ECCSTEPS/TOTAL from hawkboard.h, but
      the spl conversion is pending (and may be merged via a different tree).
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      25efd99d
  8. 26 Oct, 2010 2 commits
    • Wolfgang Denk's avatar
      Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value · 25ddd1fb
      Wolfgang Denk authored
      
      
      CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not
      being able to use "sizeof(struct global_data)" in assembler files.
      Recent experience has shown that manual synchronization is not
      reliable enough.  This patch renames CONFIG_SYS_GBL_DATA_SIZE into
      GENERATED_GBL_DATA_SIZE which gets automatically generated by the
      asm-offsets tool.  In the result, all definitions of this value can be
      deleted from the board config files.  We have to make sure that all
      files that reference such data include the new <asm-offsets.h> file.
      
      No other changes have been done yet, but it is obvious that similar
      changes / simplifications can be done for other, related macro
      definitions as well.
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      25ddd1fb
    • Wolfgang Denk's avatar
      Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE · 553f0982
      Wolfgang Denk authored
      
      
      CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be
      some end address; to make the meaning more clear we rename it into
      CONFIG_SYS_INIT_RAM_SIZE
      
      No other code changes are performed in this patch, only minor editing
      of white space (due to the changed length) and the comments was done,
      where noticed.
      
      Note that the code for the PATI and cmi_mpc5xx board configurations
      looks seriously broken.  Last known maintainers on Cc:
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      Cc: Denis Peter <d.peter@mpl.ch>
      Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch>
      Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
      553f0982
  9. 18 Oct, 2010 1 commit
  10. 23 Sep, 2010 1 commit
    • Stefan Roese's avatar
      ppc4xx: Use common NS16550 driver for PPC4xx UART · 550650dd
      Stefan Roese authored
      
      
      This patch removes the PPC4xx UART driver. Instead the common NS16550
      driver is used, since all PPC4xx SoC's use this peripheral device.
      
      The file 4xx_uart.c now only implements the UART clock calculation
      function which also sets the SoC internal UART divisors.
      
      All PPC4xx board config headers are changed to use this common NS16550
      driver now.
      
      Tested on these boards:
      acadia, canyonlands, katmai, kilauea, sequoia, zeus
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      550650dd
  11. 19 Sep, 2010 1 commit
  12. 23 Jul, 2010 1 commit
  13. 09 Nov, 2009 1 commit
    • Stefan Roese's avatar
      ppc4xx: Canyonlands: Change EBC bus config to drive always (no high-z) · 916ed944
      Stefan Roese authored
      
      
      This patch fixes a problem only seen very occasionally on Canyonlands.
      The NOR flash interface (CFI driver) doesn't work reliably in all cases.
      Erasing and/or programming sometimes doesn't work. Sometimes with
      an error message, like "flash not erased" when trying to program an
      area that should have just been erased. And sometimes without any error
      messages. As mentioned above, this problem was only seen rarely and with
      some PLL configuration (CPU speed, EBC speed).
      
      Now I spotted this problem a few times, when running my Canyonlands with
      the following setup (chip_config):
      
      1000-nor         - NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100
      
      Changing the EBC configuration to not release the bus into high
      impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
      in EBC0_CFG) seems to fix this problem. I haven't seen any failure
      anymore with this patch applied.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: David Mitchell <dmitchell@amcc.com>
      Cc: Jeff Mann <MannJ@embeddedplanet.com>
      916ed944
  14. 18 Aug, 2009 1 commit
    • Stefan Roese's avatar
      ppc4xx: Fix "chip_config" command for AMCC Arches · 514bab66
      Stefan Roese authored
      
      
      This patch fixes the "chip_config" command for I2C bootstrap EEPROM
      configuration. First it changes the I2C bootstrap EEPROM address to
      0x54 as this is used on Arches (instead of 0x52 on Canyonlands/
      Glacier). Additionally, the NAND bootstrap settings are removed
      for Arches since Arches doesn't support NAND-booting.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      514bab66
  15. 24 Jul, 2009 1 commit
    • Stefan Roese's avatar
      Add "chip_config" command for PPC4xx bootstrap configuration · 87c0b729
      Stefan Roese authored
      
      
      This patch adds a generic command for programming I2C bootstrap
      eeproms on PPC4xx. An implementation for Canyonlands board is
      included.
      
      The command name is intentionally chosen not to be PPC4xx specific.
      This way other CPU's/SoC's can implement a similar command under
      the same name, perhaps with a different syntax.
      
      Usage on Canyonlands:
      
      => chip_config
      Available configurations (I2C address 0x52):
      600-nor          - NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100
      600-nand         - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100
      800-nor          - NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100
      800-nand         - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100
      1000-nor         - NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100
      1000-nand        - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100
      1066-nor         - NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88 ***
      1066-nand        - NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88
      => chip_config 600-nor
      Using configuration:
      600-nor          - NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100
      done (dump via 'i2c md 52 0.1 10')
      Reset the board for the changes to take effect
      
      Other 4xx boards will be migrated to use this command soon
      as well.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarDirk Eibach <eibach@gdsys.de>
      Acked-by: default avatarMatthias Fuchs <matthias.fuchs@esd.eu>
      87c0b729
  16. 19 Jul, 2009 1 commit
    • Kazuaki Ichinohe's avatar
      Canyonlands SATA harddisk driver · e405afab
      Kazuaki Ichinohe authored
      This patch adds a SATA harddisk driver for the canyonlands.
      This patch is kernel driver's porting.
      This patch corresponded to not cmd_scsi but cmd_sata.
      This patch divided an unused member with ifndef __U_BOOT__ in the structure.
      
      [environment variable, boot script]
      setenv bootargs root=/dev/sda7 rw
      setenv bootargs ${bootargs} console=ttyS0,115200
      ext2load sata 0:2 0x400000 /canyonlands/uImage
      ext2load sata 0:2 0x800000 /canyonlands/canyonlands.dtb
      fdt addr 0x800000 0x4000
      bootm 0x400000 - 0x800000
      
      If you drive SATA-2 disk on Canyonlands, you must change parts from
      PI2PCIE212 to PI2PCIE2212 on U25. We confirmed to boot by using
      following disks:
      
      1.Vendor: Fujitsu	 Type: MHW2040BS
      2.Vendor: Fujitsu	 Type: MHW2060BK
      3.Vendor: HAGIWARA SYS-COM:HFD25S-032GT
      4.Vendor: WesternDigital Type: WD3200BJKT (CONFIG_LBA48 required)
      5.Vendor: WesternDigital Type: WD3200BEVT (CONFIG_LBA48 required)
      6.Vendor: Hitachi	 Type: HTS543232L9A300 (CONFIG_LBA48 required)
      7.Vendor: Seagate	 Type: ST31000333AS (CONFIG_LBA48 required)
      8.Vendor: Transcend	 Type: TS32GSSD25S-M
      9.Vendor: MTRON		 Type: MSD-SATA1525-016
      
      Signed-off-by: Kazuaki Ichinohe <kazuichi at fsi.co.jp>
      e405afab
  17. 08 Jul, 2009 1 commit
  18. 23 Jan, 2009 1 commit
  19. 21 Nov, 2008 1 commit
  20. 31 Oct, 2008 1 commit
  21. 21 Oct, 2008 1 commit
  22. 18 Oct, 2008 1 commit
  23. 14 Oct, 2008 1 commit
  24. 10 Sep, 2008 3 commits
  25. 12 Aug, 2008 1 commit
  26. 06 Jun, 2008 1 commit
    • Stefan Roese's avatar
      ppc4xx: Unify AMCC's board config files (part 2/3) · 490f2040
      Stefan Roese authored
      
      
      This patch series unifies the AMCC eval board ports by introducing
      a common include header for all AMCC eval boards:
      
      include/configs/amcc-common.h
      
      This header now includes all common configuration options/defines which
      are removed from the board specific headers.
      
      The reason for this is ease of maintenance and unified look and feel
      of all AMCC boards.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      490f2040
  27. 22 Apr, 2008 1 commit
    • Stefan Roese's avatar
      ppc4xx: Fix Canyonlands and Glacier default environment for fdt usage · 5d40d443
      Stefan Roese authored
      
      
      This patch fixes the Canyonlands and Glacier default environment to better
      fit to the arch/powerpc device-tree kernels. The variables dealing with
      arch/ppc booting are removed, since these boards are supported only in
      arch/powerpc. Glacier uses the same config file as Canyonlands.
      
      Also, the Glacier now uses non-FPU rootpath, since 460GT has no FPU.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      5d40d443
  28. 18 Apr, 2008 1 commit
  29. 09 Apr, 2008 1 commit
  30. 28 Mar, 2008 1 commit
  31. 27 Mar, 2008 1 commit
  32. 15 Mar, 2008 3 commits