1. 05 Oct, 2009 4 commits
  2. 03 Oct, 2009 2 commits
  3. 02 Oct, 2009 3 commits
    • Matthias Fuchs's avatar
      ppc4xx: Add SDRAM detection for PMC440 boards · 3b4bd2d7
      Matthias Fuchs authored
      This patch adds support to detect the amount of DDR2 SDRAM
      on PMC440 modules. Detection is done by probing through
      a list of available and supported hardware configurations
      from 1GByte down to 256MB.
      The static TLB entry is replaced by dynamically created entries.
      Signed-off-by: default avatarMatthias Fuchs <matthias.fuchs@esd.eu>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
    • Stefan Roese's avatar
      ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling · fb95169e
      Stefan Roese authored
      This patch merges the ECC handling (ECC parity byte writing) into one
      file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
      This exception is because only those PPC's use the completely different
      Denali SDRAM controller core.
      Previously we had two routines to generate/write the ECC parity bytes.
      With this patch we now only have one core function left.
      Tested on Kilauea (no ECC) and Katmai (with and without ECC).
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Felix Radensky <felix@embedded-sol.com>
      Cc: Grant Erickson <gerickson@nuovations.com>
      Cc: Pieter Voorthuijsen <pv@prodrive.nl>
    • Felix Radensky's avatar
      ppc4xx: Reorganize DDR2 ECC handling · d24bd251
      Felix Radensky authored
      Reorganize DDR2 ECC handling to use common code for
      SPD DIMMs and soldered SDRAM. Also, use common code
      to display SDRAM info (ECC, CAS latency) for SPD and
      soldered SDRAM variants.
      Signed-off-by: default avatarFelix Radensky <felix@embedded-sol.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
  4. 30 Sep, 2009 15 commits
  5. 29 Sep, 2009 1 commit
  6. 28 Sep, 2009 11 commits
  7. 27 Sep, 2009 1 commit
    • Kim Phillips's avatar
      mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields · c7190f02
      Kim Phillips authored
      some LCRR bits are not documented throughout the 83xx family RMs.
      New board porters copying similar board configurations might omit
      setting e.g., DBYP since it was not documented in their SoC's RM.
      Prevent them bricking their board by retaining power on reset values
      in bit fields that the board porter doesn't explicitly configure
      via CONFIG_SYS_<registername>_<bitfield> assignments in the board
      config file.
      also move LCRR assignment to cpu_init_r[am] to help ensure no
      transactions are being executed via the local bus while CLKDIV is being
      also start to use i/o accessors.
      Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
  8. 25 Sep, 2009 3 commits