1. 16 Sep, 2016 12 commits
  2. 07 Sep, 2016 5 commits
  3. 06 Sep, 2016 7 commits
    • Tom Rini's avatar
      TI: Rework SRAM definitions and maximums · fa2f81b0
      Tom Rini authored
      On all TI platforms the ROM defines a "downloaded image" area at or near
      the start of SRAM which is followed by a reserved area.  As it is at
      best bad form and at worst possibly harmful in corner cases to write in
      this reserved area, we stop doing that by adding in the define
      NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
      area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
      At current we define the end of scratch space at 0x228 bytes past the
      start of scratch space this this gives us a lot of room to grow.  As
      these scratch uses are non-optional today, all targets are modified to
      respect this boundary.
      
      Tested on OMAP4 Pandaboard, OMAP3 Beagle xM
      
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Nagendra T S <nagendra@mistralsolutions.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Cc: Lokesh Vutla <lokeshvutla@ti.com>
      Cc: Felipe Balbi <balbi@ti.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Paul Kocialkowski <contact@paulk.fr>
      Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Thomas Weber <weber@corscience.de>
      Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
      Cc: Thomas Chou <thomas@wytron.com.tw>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      Cc: Sam Protsenko <semen.protsenko@linaro.org>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Samuel Egli <samuel.egli@siemens.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
      Cc: Ben Whitten <ben.whitten@gmail.com>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Mugunthan V N <mugunthanvnm@ti.com>
      Cc: "B, Ravi" <ravibabu@ti.com>
      Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Ash Charles <ashcharles@gmail.com>
      Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
      Cc: Daniel Allred <d-allred@ti.com>
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      Tested-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Acked-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Tested-by: default avatarLadislav Michl <ladis@linux-mips.org>
      fa2f81b0
    • Beniamino Galvani's avatar
      meson: odroid-c2: enable Ethernet support through the device tree · cfe25561
      Beniamino Galvani authored
      Remove the device definition from board file, update the driver with
      the new compatible property and update config with necessary options.
      Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      cfe25561
    • Beniamino Galvani's avatar
      arm: dts: update DTS files for meson-gxbb and odroid-c2 · dd83840e
      Beniamino Galvani authored
      Import DTS files and dt-bindings includes from Linux 4.8-rc1.
      Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      dd83840e
    • Alexander Graf's avatar
      bcm2835_gpio: Implement GPIOF_FUNC · 04a993fe
      Alexander Graf authored
      So far we could only tell the gpio framework that a GPIO was mapped as input or
      output, not as alternative function.
      
      This patch adds support for determining whether a function is mapped as
      alternative.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Acked-by: default avatarStephen Warren <swarren@wwwdotorg.org>
      04a993fe
    • Fabio Estevam's avatar
      mx6: ddr: Allow changing REFSEL and REFR fields · edf00937
      Fabio Estevam authored
      Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
      REFR fields of the MDREF register as 1 and 7, respectively for
      DDR3 and 0 and 3 for LPDDR2.
      
      Looking at the MDREF initialization done via DCD we see that
      boards do need to initialize these fields differently:
      
      $ git grep 0x021b0020 board/
      board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
      board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
      board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
      board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
      board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
      board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
      board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
      board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
      board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
      
      So introduce a mechanism for users to be able to configure
      REFSEL and REFR fields as needed.
      
      Keep all the mx6 SPL users in their current REF_SEL and REFR values,
      so no functional changes for the existing users.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      Reviewed-by: default avatarEric Nelson <eric@nelint.com>
      edf00937
    • Akshay Bhat's avatar
      arm: imx: Add support for Advantech DMS-BA16 board · ff383220
      Akshay Bhat authored
      Add support for Advantech DMS-BA16 board. The board is based on Advantech
      BA16 module which has a i.MX6D processor. The board supports:
       - FEC Ethernet
       - USB Ports
       - SDHC and MMC boot
       - SPI NOR
       - LVDS and HDMI display
      
      Basic information about the module:
       - Module manufacturer: Advantech
       - CPU: Freescale ARM Cortex-A9 i.MX6D
       - SPECS:
           Up to 2GB Onboard DDR3 Memory;
           Up to 16GB Onboard eMMC NAND Flash
           Supports OpenGL ES 2.0 and OpenVG 1.1
           HDMI, 24-bit LVDS
           1x UART, 2x I2C, 8x GPIO,
           4x Host USB 2.0 port, 1x USB OTG port,
           1x micro SD (SDHC),1x SDIO, 1x SATA II,
           1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
      Signed-off-by: default avatarAkshay Bhat <akshay.bhat@timesys.com>
      Cc: u-boot@lists.denx.de
      Cc: sbabic@denx.de
      ff383220
    • Mugunthan V N's avatar
      ARM: dts: dra72-evm: fix broken ethernet · 0068dd68
      Mugunthan V N authored
      With commit ceec08f5, phy is connected to slave 0, but
      changing the phy node was missed, fix it by populating the
      phy node to proper cpsw slave node.
      
      Fixes: ceec08f5 ("ARM: dts: dra72-evm: Add mode-gpios entry for mac node")
      Signed-off-by: default avatarMugunthan V N <mugunthanvnm@ti.com>
      Cc: Vignesh R <vigneshr@ti.com>
      Tested-by: default avatarTom Rini <trini@konsulko.com>
      0068dd68
  4. 03 Sep, 2016 5 commits
  5. 01 Sep, 2016 1 commit
  6. 30 Aug, 2016 1 commit
    • Stephen Warren's avatar
      ARM: tegra: use numeric versioning for p2771-0000 · 7932d3e4
      Stephen Warren authored
      The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric
      versioning scheme, with version numbers such as 000/100/200/300/400/500.
      Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00.
      However, that numbering scheme is not easily visible outside of NVIDIA,
      and so does not make much sense to use. Convert U-Boot to use the readily
      visible numeric scheme.
      
      Also, it turns out that the current A02 DT actually applies to board
      versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200
      so that all U-Boot builds are named after the first version of the HW they
      support.
      Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
      Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
      7932d3e4
  7. 28 Aug, 2016 3 commits
  8. 26 Aug, 2016 6 commits
    • Masahiro Yamada's avatar
      treewide: fix "followings" to "following" · c21fc7e2
      Masahiro Yamada authored
      Most of them are my mistakes.
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      c21fc7e2
    • Stefan Agner's avatar
      arm: cache: always flush cache line size for page table · 8f894a4d
      Stefan Agner authored
      The page table is maintained by the CPU, hence it is safe to always
      align cache flush to a whole cache line size. This allows to use
      mmu_page_table_flush for a single page table, e.g. when configure
      only small regions through mmu_set_region_dcache_behaviour.
      Signed-off-by: default avatarStefan Agner <stefan.agner@toradex.com>
      Tested-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Reviewed-by: default avatarHeiko Schocher <hs@denx.de>
      8f894a4d
    • Stefan Agner's avatar
      arm: cache: add support for LPAE for region D$ behavior · c5b3cabf
      Stefan Agner authored
      Add LPAE support for mmu_set_region_dcache_behaviour. The function
      is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
      Signed-off-by: default avatarStefan Agner <stefan.agner@toradex.com>
      c5b3cabf
    • Tom Rini's avatar
      arch/arm/Kconfig: Whitespace correction · e009bfa4
      Tom Rini authored
      Use a tab not 8 spaces.
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      e009bfa4
    • Tom Rini's avatar
      ARM: Move SYS_CACHELINE_SIZE over to Kconfig · 067716ba
      Tom Rini authored
      This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
      cases we are mirroring the values used by the Linux Kernel here.  Also,
      so long as (and in this case, it is true) we implement flushes in hunks
      that are no larger than the smallest implementation (and given that we
      mirror the Linux Kernel, again we are fine) it is OK to align higher.
      The biggest changes here are that we always use 64 bytes for CPU_V7 even
      if for example the underlying core is only 32 bytes (this mirrors
      Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
      Linux Kernel) as we do not need multi-platform support (to this degree)
      and only the Cavium ThunderX 88xx series has a use for such large
      alignment.
      
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Prafulla Wadaskar <prafulla@marvell.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Nagendra T S <nagendra@mistralsolutions.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Acked-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Cc: Steve Rae <steve.rae@raedomain.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Stefan Agner <stefan.agner@toradex.com>
      Acked-by: default avatarHeiko Schocher <hs@denx.de>
      Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
      Cc: Peter Griffin <peter.griffin@linaro.org>
      Acked-by: default avatarPaul Kocialkowski <contact@paulk.fr>
      Cc: Anatolij Gustschin <agust@denx.de>
      Acked-by: default avatar"Pali Rohár" <pali.rohar@gmail.com>
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Cc: Grazvydas Ignotas <notasas@gmail.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Robert Baldyga <r.baldyga@samsung.com>
      Cc: Minkyu Kang <mk7.kang@samsung.com>
      Cc: Thomas Weber <weber@corscience.de>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: David Feng <fenghua@phytium.com.cn>
      Cc: Alison Wang <b18965@freescale.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: York Sun <york.sun@nxp.com>
      Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
      Cc: Mingkai Hu <mingkai.hu@nxp.com>
      Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
      Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
      Cc: Saksham Jain <saksham.jain@nxp.com>
      Cc: Qianyu Gong <qianyu.gong@nxp.com>
      Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
      Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
      Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
      Cc: tang yuantian <Yuantian.Tang@freescale.com>
      Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
      Cc: Josh Wu <josh.wu@atmel.com>
      Cc: Bo Shen <voice.shen@atmel.com>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
      Cc: Thomas Chou <thomas@wytron.com.tw>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      Cc: Sam Protsenko <semen.protsenko@linaro.org>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Cc: Christophe Ricard <christophe-h.ricard@st.com>
      Cc: Anand Moon <linux.amoon@gmail.com>
      Cc: Beniamino Galvani <b.galvani@gmail.com>
      Cc: Carlo Caione <carlo@endlessm.com>
      Cc: huang lin <hl@rock-chips.com>
      Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
      Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
      Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
      Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
      Cc: Kever Yang <kever.yang@rock-chips.com>
      Cc: Samuel Egli <samuel.egli@siemens.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Ian Campbell <ijc@hellion.org.uk>
      Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
      Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Ben Whitten <ben.whitten@gmail.com>
      Cc: Tom Warren <twarren@nvidia.com>
      Cc: Alexander Graf <agraf@suse.de>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Vitaly Andrianov <vitalya@ti.com>
      Cc: "Andrew F. Davis" <afd@ti.com>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Carlos Hernandez <ceh@ti.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Ash Charles <ashcharles@gmail.com>
      Cc: Mugunthan V N <mugunthanvnm@ti.com>
      Cc: Daniel Allred <d-allred@ti.com>
      Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: default avatarChin Liang See <clsee@altera.com>
      Tested-by: default avatarStephen Warren <swarren@nvidia.com>
      Acked-by: default avatarPaul Kocialkowski <contact@paulk.fr>
      067716ba
    • Jens Kuske's avatar
      sunxi: Tune H3 DRAM PLL to improve lock time · d5ac6eef
      Jens Kuske authored
      The H3 PLL5 used for DRAM barely manages to lock to the required
      frequency before DRAM controller starts, sometimes leading to wrong
      delay-line calibration results.
      This patch changes the PLL tuning parameters to the same values as
      boot0 used, which speeds up the locking and fixes the problem.
      Signed-off-by: default avatarJens Kuske <jenskuske@gmail.com>
      Reviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
      Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
      d5ac6eef