1. 27 Mar, 2008 13 commits
    • Stefan Roese's avatar
      ppc4xx: Enable ECC on LWMON5 · 7e4a0d25
      Stefan Roese authored
      
      
      Since all ECC related problems seem to be resolved on LWMON5, this patch
      now enables ECC support.
      
      We have to write the ECC bytes by zeroing and flushing in smaller
      steps, since the whole 256MByte takes too long for the external
      watchdog.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      7e4a0d25
    • Larry Johnson's avatar
      ppc4xx: Updates to Korat-specific code · 6433fa20
      Larry Johnson authored
      
      
      This patch contains updates for changes for the Korat PPC440EPx board.
      These changes include:
      
      (1) Support for "permanent" and "upgradable" copies of U-Boot, as
      described in the new "doc/README.korat" file;
      
      (2) a new memory map for the registers in the board's CPLD;
      
      (3) a revised format for manufacturer's data in serial EEPROM; and
      
      (4) changes to track updates to U-Boot for the Sequoia board.
      
      Signed-off-by: default avatarLarry Johnson <lrj@acm.org>
      6433fa20
    • Markus Brunner's avatar
      ppc4xx: PPC405EP Set EMAC noise filter bits · f766cdf8
      Markus Brunner authored
      This bug was introduced with commit aee747f1
      
      
      which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally
      disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set.
      
      Signed-off-by: default avatarMarkus Brunner <super.firetwister@gmail.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      f766cdf8
    • Mike Nuss's avatar
      ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPx · f66e2c8b
      Mike Nuss authored
      
      
      On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured
      after startup to change the speed of the clocks. This patch adds the
      option CFG_PLL_RECONFIG. If this option is set to 667, the CPU
      initialization code will reconfigure the PLL to run the system with a CPU
      frequency of 667MHz and PLB frequency of 166MHz, without the need for an
      external EEPROM.
      
      Signed-off-by: default avatarMike Nuss <mike@terascala.com>
      Acked-by: default avatarStefan Roese <sr@denx.de>
      f66e2c8b
    • Stefan Roese's avatar
      6fb4b640
    • Stefan Roese's avatar
      ppc4xx: Add fdt support to Prodrive alpr · 9462732a
      Stefan Roese authored
      
      
      Since this board will probably be ported to arch/powerpc in the
      near future, we add device tree support now. This way we are
      "ready" for arch/powerpc from now on.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      9462732a
    • Pieter Voorthuijsen's avatar
    • Stefan Roese's avatar
      ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched" · 14f73ca6
      Stefan Roese authored
      
      
      If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
      memory area will get subtracted from the top (end) of ram and won't get
      "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
      should gets passed the now "corrected" memory size and won't touch it
      either. This should work for arch/ppc and arch/powerpc. Only Linux board
      ports in arch/powerpc with bootwrapper support, which recalculate the
      memory size from the SDRAM controller setup, will have to get fixed
      in Linux additionally.
      
      This patch enables this config option on some PPC440EPx boards as a workaround
      for the CHIP 11 errata. Here the description from the AMCC documentation:
      
      CHIP_11: End of memory range area restricted access.
      Category: 3
      
      Overview:
      The 440EPx DDR controller does not acknowledge any
      transaction which is determined to be crossing over the
      end-of-memory-range boundary, even if the starting address is
      within valid memory space. Any such transaction from any PLB4
      master will result in a PLB time-out on PLB4 bus.
      
      Impact:
      In case of such misaligned bursts, PLB4 masters will not
      retrieve any data at all, just the available data up to the
      end of memory, especially the 440 CPU. For example, if a CPU
      instruction required an operand located in memory within the
      last 7 words of memory, the DCU master would burst read 8
      words to update the data cache and cross over the
      end-of-memory-range boundary. Such a DCU read would not be
      answered by the DDR controller, resulting in a PLB4 time-out
      and ultimately in a Machine Check interrupt. The data would
      be inaccessible to the CPU.
      
      Workaround:
      Forbid any application to access the last 256 bytes of DDR
      memory. For example, make your operating system believe that
      the last 256 bytes of DDR memory are absent. AMCC has a patch
      that does this, available for Linux.
      
      This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
      lwmon5, korat, sequoia
      
      The other remaining 440EPx board were intentionally not included
      since it is not clear to me, if they use the end of ram for some
      other purpose. This is unclear, since these boards have CONFIG_PRAM
      defined and even comments like this:
      
      PMC440.h:
      /* esd expects pram at end of physical memory.
       * So no logbuffer at the moment.
       */
      
      It is strongly recommended to not use the last 256 bytes on those
      boards too. Patches from the board maintainers are welcome.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      14f73ca6
    • Stefan Roese's avatar
      c664bf8c
    • Stefan Roese's avatar
      ppc4xx: Correctly pass phyiscal FLASH base address into dtb · d56a3ce1
      Stefan Roese authored
      
      
      The routine ft_board_setup() configures the EBC NOR mappings for the
      Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from
      0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS
      problem, we need to pass the corrected address here too.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      d56a3ce1
    • Stefan Roese's avatar
      ppc4xx: Fix compilation warning in 4xx_enet.c · 9ad31989
      Stefan Roese authored
      
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      9ad31989
    • Stefan Roese's avatar
      ppc4xx: Add AMCC Glacier 406GT eval board support · 4c9e8557
      Stefan Roese authored
      
      
      This patch adds support for the AMCC Glacier 460GT eval board.
      The main difference to the Canyonlands board are listed here:
      
      - 4 ethernet ports instead of 2
      - no SATA port
      - no USB port
      
      Currently EMAC2+3 are not working. This will be fixed in a later
      release.
      
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      4c9e8557
    • Stefan Roese's avatar
  2. 26 Mar, 2008 27 commits