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  1. 27 Mar, 2008 2 commits
    • Stefan Roese's avatar
      ppc4xx: Enable ECC on LWMON5 · 7e4a0d25
      Stefan Roese authored 
      

Since all ECC related problems seem to be resolved on LWMON5, this patch
now enables ECC support.

We have to write the ECC bytes by zeroing and flushing in smaller
steps, since the whole 256MByte takes too long for the external
watchdog.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
      7e4a0d25
    • Stefan Roese's avatar
      ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched" · 14f73ca6
      Stefan Roese authored 
      

If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
memory area will get subtracted from the top (end) of ram and won't get
"touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
should gets passed the now "corrected" memory size and won't touch it
either. This should work for arch/ppc and arch/powerpc. Only Linux board
ports in arch/powerpc with bootwrapper support, which recalculate the
memory size from the SDRAM controller setup, will have to get fixed
in Linux additionally.

This patch enables this config option on some PPC440EPx boards as a workaround
for the CHIP 11 errata. Here the description from the AMCC documentation:

CHIP_11: End of memory range area restricted access.
Category: 3

Overview:
The 440EPx DDR controller does not acknowledge any
transaction which is determined to be crossing over the
end-of-memory-range boundary, even if the starting address is
within valid memory space. Any such transaction from any PLB4
master will result in a PLB time-out on PLB4 bus.

Impact:
In case of such misaligned bursts, PLB4 masters will not
retrieve any data at all, just the available data up to the
end of memory, especially the 440 CPU. For example, if a CPU
instruction required an operand located in memory within the
last 7 words of memory, the DCU master would burst read 8
words to update the data cache and cross over the
end-of-memory-range boundary. Such a DCU read would not be
answered by the DDR controller, resulting in a PLB4 time-out
and ultimately in a Machine Check interrupt. The data would
be inaccessible to the CPU.

Workaround:
Forbid any application to access the last 256 bytes of DDR
memory. For example, make your operating system believe that
the last 256 bytes of DDR memory are absent. AMCC has a patch
that does this, available for Linux.

This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
lwmon5, korat, sequoia

The other remaining 440EPx board were intentionally not included
since it is not clear to me, if they use the end of ram for some
other purpose. This is unclear, since these boards have CONFIG_PRAM
defined and even comments like this:

PMC440.h:
/* esd expects pram at end of physical memory.
 * So no logbuffer at the moment.
 */

It is strongly recommended to not use the last 256 bytes on those
boards too. Patches from the board maintainers are welcome.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
      14f73ca6
  3. 18 Mar, 2008 3 commits
  5. 06 Mar, 2008 1 commit
  7. 22 Feb, 2008 1 commit
    • Yuri Tikhonov's avatar
      lwmon5: enable hardware watchdog · 2e721094
      Yuri Tikhonov authored 
      

Some boards (e.g. lwmon5) may use rather small watchdog intervals, so
causing it to reboot the board if U-Boot does a long busy-wait with
udelay(). Thus, for these boards we have to restart WD more
frequently.

This patch splits the busy-wait udelay() into smaller, predefined,
intervals, so that the watchdog timer may be resetted with the
configurable (CONFIG_WD_PERIOD) interval.

Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
      2e721094
  9. 15 Jan, 2008 1 commit
  11. 11 Jan, 2008 1 commit
  13. 09 Jan, 2008 1 commit
  15. 27 Dec, 2007 1 commit
  17. 15 Nov, 2007 1 commit
  19. 31 Oct, 2007 1 commit
  21. 23 Oct, 2007 1 commit
  23. 02 Oct, 2007 1 commit
  25. 27 Sep, 2007 1 commit
  27. 29 Aug, 2007 1 commit
  29. 24 Aug, 2007 2 commits
  31. 23 Aug, 2007 1 commit
    • Stefan Roese's avatar
      ppc4xx: Add support for 2nd I2C EEPROM on lwmon5 board · c25dd8fc
      Stefan Roese authored 
      

This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
board. Now the "eeprom" command can be used to read/write from/to this
device. Additionally a new command was added "eepromwp" to en-/disable
the write-protect of this 2nd EEPROM.

The 1st EEPROM is not affected by this write-protect command.

Signed-off-by: default avatarStefan Roese <sr@denx.de>
      c25dd8fc
  33. 22 Aug, 2007 1 commit
  35. 21 Aug, 2007 1 commit
  37. 18 Aug, 2007 1 commit
  39. 10 Aug, 2007 1 commit
  41. 31 Jul, 2007 1 commit
  43. 26 Jul, 2007 1 commit
  45. 24 Jul, 2007 1 commit
  47. 20 Jul, 2007 1 commit
  49. 10 Jul, 2007 1 commit
  51. 08 Jul, 2007 1 commit
  53. 06 Jul, 2007 2 commits
  55. 04 Jul, 2007 1 commit
    • Stefan Roese's avatar
      ppc4xx: Update lwmon5 board · 04e6c38b
      Stefan Roese authored 
      

- Add optional ECC generation routine to preserve existing
  RAM values. This is needed for the Linux log-buffer support
- Add optional DDR2 setup with CL=4
- GPIO50 not used anymore
- Lime register setup added

Signed-off-by: default avatarStefan Roese <sr@denx.de>
      04e6c38b
  57. 25 Jun, 2007 1 commit
  59. 22 Jun, 2007 1 commit
  61. 15 Jun, 2007 2 commits
  63. 01 Jun, 2007 1 commit
  65. 07 May, 2007 1 commit
  67. 05 May, 2007 1 commit