1. 20 Apr, 2016 9 commits
    • Marek Vasut's avatar
      ddr: altera: Staticize global variables · 85f76628
      Marek Vasut authored
      
      
      Just staticize global variables in sequencer, since there is no
      point in having these symbols available outside of the DDR code.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      85f76628
    • Marek Vasut's avatar
      ddr: altera: Make DLEVEL behavior inclusive · ea9aa241
      Marek Vasut authored
      
      
      Originally, the DLEVEL selects the debug level within the sequencer code,
      but only displays the messages on that particular debug level. Tweak the
      handling such that for particular debug level, debug messages on that
      level and lower are displayed. This allows better regulation of debug
      message verbosity.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      ea9aa241
    • Marek Vasut's avatar
      ddr: altera: Zero DM IN delay in scc_mgr_zero_group() · 70ed80af
      Marek Vasut authored
      
      
      This one last set of delay configuration registers was not properly
      zeroed out originally, fix it and zero them out.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      70ed80af
    • Marek Vasut's avatar
      ddr: altera: Remove unnecessary ODT mode config · f3f777cd
      Marek Vasut authored
      
      
      There is no point in resetting the ODT setting if the write test
      failed, since the code will always retry the calibration and thus
      reconfigure the ODT anyway OR the code will fail calibration and
      halt.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      f3f777cd
    • Marek Vasut's avatar
      ddr: altera: Remove unnecessary update of the SCC · f5f8c411
      Marek Vasut authored
      
      
      Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
      followed by SCC manager update. Moreover, only this function
      triggers the SCC manager update internally. Thus, remove the
      internal invocation to avoid triggering the update twice.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      f5f8c411
    • Marek Vasut's avatar
      ddr: altera: Fix DRAM end value in protection rule · 164eb23f
      Marek Vasut authored
      
      
      The hi address bitfield in the protection rule must be set to
      the last address in the region which the rule represents. The
      behavior is now in-line with code generated by Quartus 15.1 .
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      164eb23f
    • Marek Vasut's avatar
      ddr: altera: Fix scc_mgr_set() argument order · 8e9e62c9
      Marek Vasut authored
      
      
      The code should be setting registers to zero, not one register to value.
      Swap the order of arguments to correct the behavior. The behavior is now
      in-line with code generated by Quartus 15.1 .
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      8e9e62c9
    • Marek Vasut's avatar
      ddr: altera: Tweak DQS tracking enable handling · bba77110
      Marek Vasut authored
      
      
      In the most unlikely case the DQS tracking was to be disabled,
      make sure we do not errornously re-enable it. Note that DQS
      tracking is enabled on all systems observed thus far.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      bba77110
    • Marek Vasut's avatar
      ddr: altera: Replace ad-hoc constant with macro · abaf8361
      Marek Vasut authored
      
      
      The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
      is a macro for this bit already, so use it.
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      abaf8361
  2. 16 Apr, 2016 1 commit
  3. 15 Apr, 2016 3 commits
  4. 14 Apr, 2016 6 commits
  5. 13 Apr, 2016 21 commits