1. 28 Aug, 2008 1 commit
    • John Rigby's avatar
      ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon · 8a490422
      John Rigby authored
      
      
      MPC5121 rev 2 silicon has a new register for controlling how long
      CS is asserted after deassertion of ALE in multiplexed mode.
      
      The default is to assert CS together with ALE.  The alternative
      is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE.
      
      The default is wrong for the NOR flash and CPLD on the ADS5121.
      
      This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD)
      it does so conditionally based on silicon rev 2.0 or greater.
      Signed-off-by: default avatarMartha J Marx <mmarx@silicontkx.com>
      Signed-off-by: default avatarJohn Rigby <jrigby@freescale.com>
      8a490422
  2. 27 Aug, 2008 39 commits