1. 16 Oct, 2015 1 commit
    • Dinh Nguyen's avatar
      arm: socfpga: enable data/inst prefetch and shared override in the L2 · 8d8e13e1
      Dinh Nguyen authored
      Update the L2 AUX CTRL settings for the SoCFPGA.
      Enabling D and I prefetch bits helps improve SDRAM performance on the
      Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
      PL310 Auxiliary Control register (shared attribute override enable) has the
      side effect of transforming Normal Shared Non-cacheable reads into Cacheable
      no-allocate reads.
      Coherent DMA buffers in Linux always have a Cacheable alias via the
      kernel linear mapping and the processor can speculatively load cache
      lines into the PL310 controller. With bit 22 cleared, Non-cacheable
      reads would unexpectedly hit such cache lines leading to buffer
      Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
  2. 15 Oct, 2015 10 commits
  3. 14 Oct, 2015 1 commit
  4. 13 Oct, 2015 1 commit
  5. 12 Oct, 2015 4 commits
  6. 11 Oct, 2015 23 commits