1. 26 Aug, 2016 12 commits
    • Stefan Agner's avatar
      arm: cache: always flush cache line size for page table · 8f894a4d
      Stefan Agner authored
      
      
      The page table is maintained by the CPU, hence it is safe to always
      align cache flush to a whole cache line size. This allows to use
      mmu_page_table_flush for a single page table, e.g. when configure
      only small regions through mmu_set_region_dcache_behaviour.
      Signed-off-by: default avatarStefan Agner <stefan.agner@toradex.com>
      Tested-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      Reviewed-by: default avatarHeiko Schocher <hs@denx.de>
      8f894a4d
    • Stefan Agner's avatar
      arm: cache: add support for LPAE for region D$ behavior · c5b3cabf
      Stefan Agner authored
      
      
      Add LPAE support for mmu_set_region_dcache_behaviour. The function
      is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
      Signed-off-by: default avatarStefan Agner <stefan.agner@toradex.com>
      c5b3cabf
    • Tom Rini's avatar
      arch/arm/Kconfig: Whitespace correction · e009bfa4
      Tom Rini authored
      
      
      Use a tab not 8 spaces.
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      e009bfa4
    • Tom Rini's avatar
      ARM: Move SYS_CACHELINE_SIZE over to Kconfig · 067716ba
      Tom Rini authored
      
      
      This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
      cases we are mirroring the values used by the Linux Kernel here.  Also,
      so long as (and in this case, it is true) we implement flushes in hunks
      that are no larger than the smallest implementation (and given that we
      mirror the Linux Kernel, again we are fine) it is OK to align higher.
      The biggest changes here are that we always use 64 bytes for CPU_V7 even
      if for example the underlying core is only 32 bytes (this mirrors
      Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
      Linux Kernel) as we do not need multi-platform support (to this degree)
      and only the Cavium ThunderX 88xx series has a use for such large
      alignment.
      
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Prafulla Wadaskar <prafulla@marvell.com>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Nagendra T S <nagendra@mistralsolutions.com>
      Cc: Vaibhav Hiremath <hvaibhav@ti.com>
      Acked-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Cc: Steve Rae <steve.rae@raedomain.com>
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Nikita Kiryanov <nikita@compulab.co.il>
      Cc: Stefan Agner <stefan.agner@toradex.com>
      Acked-by: default avatarHeiko Schocher <hs@denx.de>
      Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
      Cc: Peter Griffin <peter.griffin@linaro.org>
      Acked-by: default avatarPaul Kocialkowski <contact@paulk.fr>
      Cc: Anatolij Gustschin <agust@denx.de>
      Acked-by: default avatar"Pali Rohár" <pali.rohar@gmail.com>
      Cc: Adam Ford <aford173@gmail.com>
      Cc: Steve Sakoman <sakoman@gmail.com>
      Cc: Grazvydas Ignotas <notasas@gmail.com>
      Cc: Nishanth Menon <nm@ti.com>
      Cc: Stephen Warren <swarren@wwwdotorg.org>
      Cc: Robert Baldyga <r.baldyga@samsung.com>
      Cc: Minkyu Kang <mk7.kang@samsung.com>
      Cc: Thomas Weber <weber@corscience.de>
      Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
      Cc: David Feng <fenghua@phytium.com.cn>
      Cc: Alison Wang <b18965@freescale.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: York Sun <york.sun@nxp.com>
      Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
      Cc: Mingkai Hu <mingkai.hu@nxp.com>
      Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
      Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
      Cc: Saksham Jain <saksham.jain@nxp.com>
      Cc: Qianyu Gong <qianyu.gong@nxp.com>
      Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
      Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
      Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
      Cc: tang yuantian <Yuantian.Tang@freescale.com>
      Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
      Cc: Josh Wu <josh.wu@atmel.com>
      Cc: Bo Shen <voice.shen@atmel.com>
      Cc: Viresh Kumar <viresh.kumar@linaro.org>
      Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
      Cc: Thomas Chou <thomas@wytron.com.tw>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      Cc: Sam Protsenko <semen.protsenko@linaro.org>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Cc: Christophe Ricard <christophe-h.ricard@st.com>
      Cc: Anand Moon <linux.amoon@gmail.com>
      Cc: Beniamino Galvani <b.galvani@gmail.com>
      Cc: Carlo Caione <carlo@endlessm.com>
      Cc: huang lin <hl@rock-chips.com>
      Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
      Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
      Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
      Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
      Cc: Kever Yang <kever.yang@rock-chips.com>
      Cc: Samuel Egli <samuel.egli@siemens.com>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Ian Campbell <ijc@hellion.org.uk>
      Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
      Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
      Cc: Wolfgang Denk <wd@denx.de>
      Cc: Ben Whitten <ben.whitten@gmail.com>
      Cc: Tom Warren <twarren@nvidia.com>
      Cc: Alexander Graf <agraf@suse.de>
      Cc: Sekhar Nori <nsekhar@ti.com>
      Cc: Vitaly Andrianov <vitalya@ti.com>
      Cc: "Andrew F. Davis" <afd@ti.com>
      Cc: Murali Karicheri <m-karicheri2@ti.com>
      Cc: Carlos Hernandez <ceh@ti.com>
      Cc: Ladislav Michl <ladis@linux-mips.org>
      Cc: Ash Charles <ashcharles@gmail.com>
      Cc: Mugunthan V N <mugunthanvnm@ti.com>
      Cc: Daniel Allred <d-allred@ti.com>
      Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: default avatarChin Liang See <clsee@altera.com>
      Tested-by: default avatarStephen Warren <swarren@nvidia.com>
      Acked-by: default avatarPaul Kocialkowski <contact@paulk.fr>
      067716ba
    • Tom Rini's avatar
      da968c7b
    • Tom Rini's avatar
      c733c18e
    • Simon Baatz's avatar
      tools: kwboot: patch destaddr only for SoCs with header version 1 · bdf58c73
      Simon Baatz authored
      Commit f4db6c97
      
       ("arm: mvebu: Add runtime detection of UART (xmodem)
      boot-mode") added a change to hdr->destaddr when dynamically patching an
      image for UART boot mode.  With this change, kwboot ceases to work on
      Kirkwood.
      
      Thus, let's change hdr->destaddr only when we are patching an image with
      header version 1 (Orion and Kirkwood use header version 0).
      Signed-off-by: default avatarSimon Baatz <gmbnomis@gmail.com>
      Fixes: f4db6c97
      
       ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode")
      Cc: Stefan Roese <sr@denx.de>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      bdf58c73
    • Chris Packham's avatar
      c90d7ab6
    • Chris Packham's avatar
      arm: mvebu: a38x: update serdes error handling · 014a357b
      Chris Packham authored
      
      
      Ensure appropriate error messages are generated. Previously all errors
      indicated that the serdes was already in use. Now appropriate error
      messages are given.
      Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      014a357b
    • Chris Packham's avatar
      spl: Remove unused CONFIG_SPL_SPI_* definitions · 148f00e7
      Chris Packham authored
      As of commit 88e34e5f
      
       ("spl: replace CONFIG_SPL_SPI_* with
      CONFIG_SF_DEFAULT_*") these defines are not used. Remove them to avoid
      confusion.
      Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      148f00e7
    • Chris Packham's avatar
      arm: mvebu: Add support for NAND interface on A-38x · d7b4731e
      Chris Packham authored
      
      
      The NAND interface on the Armada-38x series is similar to that on the
      Armada-XP. The key difference is that the NAND ECC clock ratio is
      provided via the DFX Server registers instead of the Core Clock.
      Signed-off-by: default avatarChris Packham <chris.packham@alliedtelesis.co.nz>
      Cc: Luka Perkov <luka.perkov@sartura.hr>
      Cc: Dirk Eibach <eibach@gdsys.de>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      d7b4731e
    • Stefan Roese's avatar
      i2c: mvtwsi: Fix order of address bytes (high to low) · 03d6cd97
      Stefan Roese authored
      Patch f8a10ed1
      
       [i2c: mvtwsi: Make address length variable] accidentally
      inverted the sequence of address bytes sent to the I2C device. This
      patch corrects this by sending the highest byte first and the lowest
      byte last again.
      
      Tested on theadorable Armada-XP board.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Mario Six <mario.six@gdsys.cc>
      Cc: Heiko Schocher <hs@denx.de>
      03d6cd97
  2. 25 Aug, 2016 4 commits
  3. 23 Aug, 2016 2 commits
  4. 22 Aug, 2016 20 commits
  5. 20 Aug, 2016 2 commits