- 05 Apr, 2017 40 commits
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Ye Li authored
Set the CONFIG_CMD_MEMTEST on all mx6 platforms for enabling the u-boot memory test. Signed-off-by:Ye Li <ye.li@nxp.com> (cherry picked from commit 75b5a7d5931064386ae38ce74a34eb6e368666a5)
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Ye Li authored
When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: -
Ye Li authored
When using watchdog timeout in kernel, the reset does not output the WDOG_B signal, so the power supply won't be reset. To solve the problem, we enable it in u-boot. Signed-off-by: -
Ye.Li authored
Set the ID pin pad to pull up not the pull down at default, otherwise we can't enter the device mode, but always detect as host. After this change we have to use portA cable to play as host, and use portB cable for device. Signed-off-by:Ye.Li <B37916@freescale.com> (cherry picked from commit b315d6b36a913d75d25284320e69050ebdf7a7eb)
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Ye Li authored
This is a demo that CM4 will boot up by u-boot without typing any command. It boots up at u-boot early init, try to minimize the time from power up to the CM4 running. Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in u-boot to avoid conflict. RDC for shared GPIO1 is added, but not enabled, because the kernel is not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to enable it. Some legacy codes in mx6sxsabreauto are removed. We only need this work on mx6sxsabresd as a demo. Signed-off-by: -
Ye Li authored
Add support for various boot devices like NAND, QSPINOR, SPINOR, eMMC, EIMNOR, SATA. Modify board level files to support the feature and add corresponding defconfig files Signed-off-by: -
Ye Li authored
CONFIG_SECURE_BOOT is used for signed image building, this configuration is not enabled at default. Comment it in mx6/mx7 common header file. Users can uncomment it to enable. Also add CONFIG_CSF_SIZE for defining the CSF reserved size and resize the CONFIG_CSF_SIZE to 0x4000 to align with v2016.03. Signed-off-by: -
Ye Li authored
To support the trust boot chain, we integrate the authentication into the kernel image loading process. The kernel image will be verified at its load address. So when signing the kernel image, we need to use this load address which may change on different platforms. Signed-off-by: -
Ye Li authored
Port LDO bypass support from v2015 to support the features: 1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages. LDO bypass is dependent on the flatten device tree file. 2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to reboot whole board, so split these code to independent function so that board file can call it freely. Signed-off-by: -
Ye Li authored
Align with imx_v2016.03 1. Update pmic settings to enable SD3 power and use PMIC common init codes. 2. Enable bmode. 3. Update MMC root parameters 4. Update AUXBOOT for M4 Signed-off-by:
Peng Fan <peng.fan@nxp.com> (cherry picked from commit 0816a496fbe3f7d0e4f1a9322c76908a5c557c8c) Signed-off-by:
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Peng Fan authored
Align with imx_v2016.03. Add emmc support which needs board rework. Add I2C2. Update pmic settings. Add bmode. Move partial code from board_early_init_f to board_init. Add PCI power and reset GPIO and disable PCI at default. Update QSPI settings. Signed-off-by: -
Peng Fan authored
Align with imx_v2016.03. Add usb ethernet support, since there is no FEC on this i.MX6UL Signed-off-by: -
Peng Fan authored
Add elan code, to handle epdc which has i2c devices. In imx_v2015.04, the two pathces are for elan. b6ba68516b681a38025252bd0ef6a6ed3e8adfa0 MLK-10215 Add elan init in i.MX6SL-EVK board 0c600f6a67f00fe0c674c08c355bea3789109679 MLK-10885 imx: mx6slevk ignore elan init when no epdc on board Signed-off-by:
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Peng Fan authored
Add default build target for mx6qp and mx6solo. Signed-off-by:
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Ye Li authored
Align board code and header file with imx_v2016.03. Update pmic settings for i.MX6QP. wrap spi code together using CONFIG_MXC_SPI macro. To i.MX6SOLO, need to define nosmp in bootargs. Signed-off-by:
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Ye Li authored
DDR script file: arik_r2_sdb_ddr3_528_1.14.inc Compass link: http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1 Update: setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10) setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00) setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10) setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10) setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10) setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10) setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10) setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10) setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 setmem /32 0x021b48c0 = 0x24914452 setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1 Test: Passed stress memtester on one board. Signed-off-by:
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Peng Fan authored
Align ddr script with imx_v2016.03 latest ddr script. mx6qp.cfg is 1.13 version http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI arik_r2_sdb_ddr3_528_1.13.inc is for sabresd Signed-off-by:
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Peng Fan authored
To Align with imx_v2016.03. 1. Add USDHC1 support on mother board 2. Add SPINOR flash support. 3. Add enet ref clk pinmux setting and enet settings 4. Use CONFIG_SYS_USE_EIMNOR to wrap eimnor settings. 5. update mmc board settings 6. update board_init and move nand settings to board_init, but not in board_early_init_f 7. update pmic settings to align with datasheet. Signed-off-by:
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Peng Fan authored
Add solo version ddr script and build target. Signed-off-by:
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Ye Li authored
For i.MX6 SOLO sabreauto and sabresd boards, add the "nosmp" kernel bootargs. Signed-off-by: -
Ye Li authored
Since there is already CONFIG_MX6S used for i.MX6 SOLO in u-boot codes, we don't need to add new CONFIG_MX6SOLO. Rename the existing CONFIG_MX6SOLO to CONFIG_MX6S. Additional, for CONFIG_MX6S, we should select CONFIG_MX6DL. The major difference for these two chips are core number and DDR controller. So all duallite relevant definitions can apply to solo. User can combine the two configs if any code only apply to solo or duallite. Signed-off-by: -
Peng Fan authored
DDR script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4 http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1 arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI Patch in imx_v2015.04: " commit 5fb08a4dcc7b8478fc4236b90ad8dc2190cf94e7 Author: Peng Fan <Peng.Fan@freescale.com> Date: Wed Nov 4 16:30:47 2015 +0800 "MLK-11825 imx: mx6dqp: update ddr script to 1.13" " Signed-off-by:
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Peng Fan authored
Define CONFIG_MMCROOT, CONFIG_SYS_MMC_ENV_PART to align with imx_v2016.03. Signed-off-by:
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Peng Fan authored
Add mx6qarm2 new board revision support using mx6q pop SoC Enable DRAM support for imx6q PoP SoC with populated LPDDR2 MT42L128M64D2 DDR calibration script: http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69 Test result: Stress test passed. Signed-off-by:
Adrian Alonso <adrian.alonso@nxp.com> (cherry picked from commit b0ac10892cad46c22accf89c04ea59c46bd9eb01)
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Peng Fan authored
ALign with imx_v2015.04. Also to lpddr2 support: From commit: "620cf5f3d4cf37b065b5857a8ea91d61bf6c471d" " Current uboot supports for running LPDDR2 at 400MHz on MX6Q ARM2 board, but there is a problem in switching pre_periph_clk_sel to pll2_pfd2. We cannot directly change the parent of pre_periph_clk_sel as this mux is not a glitchless mux. We need to follow the correct procedure and wait for the busy bits to clear before switching. Change to follow the procedure: 1. Set periph_clk2 to OSC. 2. Switch the periph_clk to periph_clk2, checking the CCM_CDHIPR for periph_clk , ahb_podf and axi_podf busy bits. 3. Setting the pre_periph_clk to PLL2 PFD 396M. 4. Switch the periph_clk back to pre_periph_clk and checking CCM_CDHIPR busy bits. " Signed-off-by:
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Peng Fan authored
Add the support for i.MX6DQ PoP lpddr2 ARM2 board. Signed-off-by: -
Ye Li authored
Add plugin.S for plugin boot initialization on mx6dq/dl arm2 board. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. New build configurations are added for the plugin: mx6dlarm2_lpddr2_plugin_defconfig mx6dlarm2_plugin_defconfig mx6qarm2_lpddr2_plugin_defconfig configs/mx6qarm2_plugin_defconfig Signed-off-by: -
Ye Li authored
Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add build configurations for the plugin: mx6ul_14x14_evk_plugin_defconfig mx6ul_9x9_evk_plugin_defconfig Signed-off-by: -
Ye Li authored
Add plugin.S for plugin boot initialization on mx6dq/dl/dqp sabresd and sabreauto boards. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the configurations for the plugin enabled buiding. Signed-off-by: -
Ye Li authored
Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the build configuration "mx6sxsabreauto_plugin_defconfig" to use the plugin. Signed-off-by: -
Ye Li authored
Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the build configuration "mx6sxsabresd_plugin_defconfig" to use the plugin. Signed-off-by: -
Ye Li authored
Add plugin.S for plugin boot initialization. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature. Add the build configuration "mx6slevk_plugin_defconfig" to use the plugin. Signed-off-by: -
Ye.Li authored
The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: -
Andy Duan authored
Specify the registered eth index by dev_id. Signed-off-by:Fugang Duan <fugang.duan@nxp.com> (cherry picked from commit df42b7b0c5e6847f32419075eb25f274ed039d6f)
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Andy Duan authored
Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(), it should transfer fec->dev_id to get mac address from fuse. Signed-off-by: -
Peng Fan authored
Use NXP logo. The vendor and board dir not changed, only replace the contents of freescale.bmp. Signed-off-by: -
Ye Li authored
The mfgtool environments only can set in BSP u-boot image, not for android u-boot. Since android u-boot may go into fastboot in board_r phase which is earlier than mfgtool environment check. The USB status from android fastboot will cause u-boot to configure mfgtool environment. Signed-off-by: -
Peng Fan authored
Update CCM macros for i.MX6SLL. Signed-off-by:
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Peng Fan authored
Update soc settings for i.MX6SLL. Signed-off-by: -
Peng Fan authored
For Some USB mass storage devices, such as: " - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA - Class: (from Interface) Mass Storage - PacketSize: 64 Configurations: 1 - Vendor: 0x0930 Product 0x6545 Version 1.16 " When `usb read 0x80000000 0 0x2000`, we met "EHCI timed out on TD - token=0x80008d80". The devices does not support scsi VPD page, we are not able to get the maximum transfer length for READ(10)/WRITE(10). So we limit this to 256 blocks as READ(6). Signed-off-by:
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