1. 05 Sep, 2014 4 commits
  2. 31 Aug, 2014 15 commits
  3. 30 Aug, 2014 13 commits
  4. 29 Aug, 2014 4 commits
  5. 25 Aug, 2014 4 commits
    • Lokesh Vutla's avatar
      ARM: DRA: Enable VTT regulator · 7b922523
      Lokesh Vutla authored
      DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
      and this is controlled by gpio7_11. Configuring gpio7_11.
      The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
      and left unused on previous boards, so it is safe enough to enable gpio
      on all DRA7 boards.
      Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
    • Sricharan R's avatar
      ARM: DRA7: Enable software leveling for dra7 · f2a1b93b
      Sricharan R authored
      Currently hw leveling is enabled by default on DRA7/72.
      But the hardware team suggested to use sw leveling as hw leveling
      is not characterized and seen some test case failures.
      So enabling sw leveling on all DRA7 platforms.
      Signed-off-by: default avatarSricharan R <r.sricharan@ti.com>
      Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
    • Vitaly Andrianov's avatar
      keystone2: use EFUSE_BOOTROM information to configure PLLs · 61f66fd5
      Vitaly Andrianov authored
      This patch reads EFUSE_BOOTROM register to see the maximum supported
      clock for CORE and TETRIS PLLs and configure them accordingly.
      Acked-by: default avatarMurali Karicheri <m-karicheri2@ti.com>
      Signed-off-by: default avatarVitaly Andrianov <vitalya@ti.com>
      Signed-off-by: default avatarIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
    • pekon gupta's avatar
      board/ti/dra7xx: add support for parallel NOR · 9352697a
      pekon gupta authored
      This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
      The Flash device is connected to GPMC controller on chip-select[0] and accessed
      as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
      is CFI compatible.
      As multiple devices are share GPMC pins on this board, so following board
      settings are required to detect NOR device:
           SW5.1 (NAND_BOOTn) = OFF (logic-1)
           SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
           SW5.3 (eMMC_BOOTn) = OFF (logic-1)
           SW5.4 (QSPI_BOOTn) = OFF (logic-1)
      And also set appropriate SYSBOOT configurations:
           SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
           SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
           SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
           SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
           SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
           SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
           SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
           SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */
      Also, following changes are required to enable NOR Flash support in
      dra7xx_evm board profile: