1. 13 Oct, 2009 11 commits
    • Prafulla Wadaskar's avatar
      Kirkwood: mv88f6281gtw_ge: Add kwbimage build support · a62e78fc
      Prafulla Wadaskar authored
      
      
      This patch adds kwbimage configuration file
      (used by mkimage utility)
      to support u-boot.kwb target on mv88f6281gtw_ge board.
      
      To create Kirkwood boot image to be flashed on SPI Flash,
      additional parameter u-boot.kwb need to be passed during make.
      Signed-off-by: default avatarPrafulla Wadaskar <prafulla@marvell.com>
      a62e78fc
    • Prafulla Wadaskar's avatar
      Kirkwood: rd6281a: Add kwbimage build support · 5bc7cbc1
      Prafulla Wadaskar authored
      
      
      This patch adds kwbimage configuration file
      (used by mkimage utility)
      to support u-boot.kwb target on rd6281a platform.
      
      To create Kirkwood boot image to be flashed on NAND,
      additional parameter u-boot.kwb need to be passed during make.
      Signed-off-by: default avatarPrafulla Wadaskar <prafulla@marvell.com>
      5bc7cbc1
    • Tom Rix's avatar
      Add support for Eukrea CPU9260/CPU9G20 SBC · 23b80982
      Tom Rix authored
      
      
      these boards are built around Atmel's AT91SAM9260/9G20 and have
      up to 64MB of NOR flash, up to 128MB of SDRAM, up to 2GB of NAND
      and include a 10/100 Ethernet PHY in RMII mode.
      Signed-off-by: default avatarEric Benard <eric@eukrea.com>
      Signed-off-by: default avatarTom Rix <Tom.Rix@windriver.com>
      23b80982
    • Tom Rix's avatar
      Add support for Eukrea CPUAT91 SBC · d8380c9d
      Tom Rix authored
      
      
      CPUAT91 is built around Atmel's AT91RM9200 and has up to 16MB of NOR
      flash, up to 128MB of SDRAM, and includes a Micrel KS8721 PHY in RMII
      mode.
      Signed-off-by: default avatarEric Benard <eric@eukrea.com>
      Signed-off-by: default avatarTom Rix <Tom.Rix@windriver.com>
      d8380c9d
    • Sandeep Paulraj's avatar
      TI: DaVinci DM365: Minor config cleanup · eb95aa15
      Sandeep Paulraj authored
      
      
      The DM365 config was using the 'CONFIG_CMD_SAVEENV' flag.
      This is already included when we include the
      config_cmd_default.h header file. So this flag is removed.
      Also another flag to enable NAND functions was being
      enabled incorrectly.
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      eb95aa15
    • Sandeep Paulraj's avatar
      TI DaVinci DM365: Removing header file which does not exist · 5d783c1f
      Sandeep Paulraj authored
      
      
      The DaVinci DM365 EVM board specific code was including a header file
      which does not exist. So removing this header file.
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      5d783c1f
    • Sandeep Paulraj's avatar
      TI DaVinci: DM355: Config Cleanup and Update · 409ec37b
      Sandeep Paulraj authored
      
      
      This patch does the following
      1) Enables the NAND driver which is now available.
      2) Enables the 'CONFIG_MTD_DEVICE' as without this the
      compilation will fail
      3) We now have a safe place to store environment and defines
      an offset where this can be stored. This offset value is such that it is after
      the location where U-Boot is flashed using TI flash utilities.
      4) Enables Bootdelay
      5) Increases malloc() arena size. Manufacturers are coming out with
      NAND with large blocks sizes of upto 1 MiB. It has been noticed that
      as the block size of the NAND used is increased, if this particular
      value is not increased, the NAND driver will output out of memory
      errors.
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      409ec37b
    • Sandeep Paulraj's avatar
      TI DaVinci: DM646x: Initial Support for DM646x SOC · 7908c97a
      Sandeep Paulraj authored
      
      
      DM646x is an SOC from TI which has both an ARM and a DSP.
      There are multiple variants of the SOC mainly dealing with different
      core speeds.
      This patch adds the initial framework for the DM646x SOC.
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      7908c97a
    • Sandeep Paulraj's avatar
      TI DaVinci: DM6446: Fix Compilation error in NAND mode · 5d0f5362
      Sandeep Paulraj authored
      
      
      The Default mode that is built for the Davinci DVEVM happens
      to be the NOR mode.
      When we want to build for the NAND mode, we get a compilation
      error. This is overcome by defining the CONFIG_MTD_DEVICE
      flag in the NAND mode.
      The image built for NAND mode was successfully tested on the
      DaVinci DM6446 EVM.
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      5d0f5362
    • Tom Rix's avatar
      OMAP3 Move cache routine to cache.S · 7a2aa8b6
      Tom Rix authored
      
      
      v7_flush_dcache_all, because it depends on omap ROM code is not
      generic.  Rename the function to 'invalidate_dcache' and move it
      to the omap cpu directory.
      
      Collect the other omap cache routines l2_cache_enable and
      l2_cache_disable with invalide_dcache into cache.S.  This
      means removing the old cache.c file that contained l2_cache_enable
      and l2_cache_disable.
      
      The conversion from cache.c to cache.S was done most through
      disassembling the uboot binary.  The only significant change was
      to change the comparision for the return of get_cpu_rev from
      
         cmp	r0, #0
         beq	earlier_than_label
      
      Which was lost information to
      
         cmp	r0, #CPU_3XX_ES20
         blt	earlier_than_label
      
      The paths through the enable routine were verified by
      adding an infinite loop and seeing the hang.  Then
      removing the infinite loop and seeing it continue.
      
      The disable routine is similar enough that it was not
      tested with this method.
      
      Run tested by cold booting from nand on beagle and zoom1.
      Compile tested on MAKEALL arm.
      Signed-off-by: default avatarTom Rix <Tom.Rix@windriver.com>
      7a2aa8b6
    • Sandeep Paulraj's avatar
      TI DaVinci: Remove references to SZ_xx · a16df2c1
      Sandeep Paulraj authored
      
      
      This patch removes the asm/sizes.h header file from being
      included in the DaVinci SOC configs.
      References to SZ_xx have been replaced by appropriate
      bit shifted values.
      Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
      Acked-by: default avatarWolfgang Denk <wd@denx.de>
      a16df2c1
  2. 12 Oct, 2009 2 commits
  3. 11 Oct, 2009 3 commits
    • Luigi 'Comio' Mantellini's avatar
    • Luigi 'Comio' Mantellini's avatar
    • Luigi 'Comio' Mantellini's avatar
      Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an... · 4ba31ab3
      Luigi 'Comio' Mantellini authored
      
      Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses.
      
      This feature is useful when your board uses different mii buses for different
      phys and all (or a part) of these buses are implemented via bit-banging mode.
      
      The driver requires that the following macros should be defined into the board
      configuration file:
      
      CONFIG_BITBANGMII       - Enable the miiphybb driver
      CONFIG_BITBANGMII_MULTI - Enable the multi bus support
      
      If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
      to define at least the following macros:
      
      MII_INIT      - Generic code to enable the MII bus (optional)
      MDIO_DECLARE  - Declaration needed to access to the MDIO pin (optional)
      MDIO_ACTIVE   - Activate the MDIO pin as out pin
      MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
      MDIO_READ     - Read the MDIO pin
      MDIO(v)       - Write v on the MDIO pin
      MDC_DECLARE   - Declaration needed to access to the MDC pin (optional)
      MDC(v)        - Write v on the MDC pin
      
      The previous macros make the driver compatible with the previous version
      (that didn't support the multi-bus).
      
      When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
      the bb_miiphy_buses[] array with a record for each required bus and declare
      the bb_miiphy_buses_num variable with the number of mii buses.
      The record (struct bb_miiphy_bus) has the following fields/callbacks (see
      miiphy.h for details):
      
      char name[]            - The symbolic name that must be equal to the MII bus
                               registered name
      int (*init)()          - Initialization function called at startup time (just
                               before the Ethernet initialization)
      int (*mdio_active)()   - Activate the MDIO pin as output
      int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
      int (*set_mdio)()      - Write the MDIO pin
      int (*get_mdio)()      - Read the MDIO pin
      int (*set_mdc)()       - Write the MDC pin
      int (*delay)()         - Delay function
      void *priv             - Private data used by board specific code
      
      The board code will look like:
      
      struct bb_miiphy_bus bb_miiphy_buses[] = {
       { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... },
       { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... },
       ...
      int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
                                sizeof(bb_miiphy_buses[0]);
      Signed-off-by: default avatarLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
      Signed-off-by: default avatarBen Warren <biggerbadderben@gmail.com>
      4ba31ab3
  4. 08 Oct, 2009 2 commits
  5. 07 Oct, 2009 10 commits
  6. 05 Oct, 2009 7 commits
  7. 03 Oct, 2009 5 commits