1. 27 Oct, 2011 1 commit
  2. 26 Oct, 2011 6 commits
  3. 21 Oct, 2011 1 commit
  4. 17 Oct, 2011 1 commit
  5. 10 Oct, 2011 1 commit
    • Xiangfu Liu's avatar
      MIPS: Ingenic XBurst Jz4740 processor support · 80421fcc
      Xiangfu Liu authored
      Jz4740 is a multimedia application processor targeting for mobile
      devices like e-Dictionary, eBook, portable media player (PMP) and
      GPS navigator.  Jz4740 is powered by Ingenic 360 MHz XBurst CPU core
      (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture
      provides high integration, high performance and low power consumption.
      JzRISC incorporated in Jz4740 is the advanced and power-efficient
      32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K
      D-Cache, and can operate at speeds up to 400 MHz.
      On-chip modules such as LCD controller, embedded audio codec, multi-
      channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich
      suite of peripherals for multimedia application.  NAND controller
      (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are
      also available.
      For more info about Ingenic XBurst Jz4740:
      This patch introduces XBurst CPU support in U-Boot.  It's compatible
      with MIPS32, but requires a bit different cache maintenance, timer
      routines, and boot mechanism using USB boot tool, so XBurst support
      can go into a separate new home, cpu/xburst/.
      Signed-off-by: default avatarXiangfu Liu <xiangfu@openmobilefree.net>
      Acked-by: default avatarDaniel <zpxu@ingenic.cn>
      Signed-off-by: default avatarShinya Kuribayashi <skuribay@pobox.com>
  6. 09 Oct, 2011 4 commits
    • York Sun's avatar
      powerpc/8xxx: Add support for interactive DDR programming interface · 6f5e1dc5
      York Sun authored
      Interactive DDR debugging provides a user interface to view and modify SPD,
      DIMM parameters, board options and DDR controller registers before DDR is
      initialized. With this feature, developers can fine-tune DDR for board
      bringup and other debugging without frequently having to reprogram the flash.
      To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
      file and set an environment variable to activate it. Syntax:
      setenv ddr_interactive on
      After reset, U-boot prompts before initializing DDR controllers
      FSL DDR>
      The available commands are
      print      print SPD and intermediate computed data
      reset      reboot machine
      recompute  reload SPD and options to default and recompute regs
      edit       modify spd, parameter, or option
      compute    recompute registers from current next_step to end
      next_step  shows current next_step
      help       this message
      go         program the memory controller and continue with u-boot
      The first command should be "compute", which reads data from DIMM SPDs and
      board options, performs the calculation then stops before setting DDR
      controller. A user can use "print" and "edit" commands to view and modify
      anything. "Go" picks up from current step with any modification and
      compltes the calculation then enables the DDR controller to continue u-boot.
      "Recompute" does it over from fresh reading.
      Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
    • Che-liang Chiou's avatar
      cmd_time: add time command · ca366d0e
      Che-liang Chiou authored
      The 'time' command runs and reports execution time of commands.
      Sample usage:
      u-boot# time crc 0x1000 1000
      CRC32 for 00001000 ... 00001fff ==> ae94dc4b
      time: 0.004 seconds, 4 ticks
      Signed-off-by: default avatarChe-Liang Chiou <clchiou@chromium.org>
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
    • Wolfgang Denk's avatar
      README: fix typos and such. · 6feff899
      Wolfgang Denk authored
      Reported-by: default avatarMichael Jones <michael.jones@matrix-vision.de>
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
    • Wolfgang Denk's avatar
      README: fix documentation of CONFIG_SHOW_BOOT_PROGRESS · 4cf2609b
      Wolfgang Denk authored
      Some previous changes added code right in the middle of the
      description of CONFIG_SHOW_BOOT_PROGRESS.  Move this text down.
      Fix formatting while we are at it.
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
  7. 05 Oct, 2011 2 commits
    • Mike Frysinger's avatar
      net: drop !NET_MULTI code · e2a53458
      Mike Frysinger authored
      This is long over due.  All but two net drivers have been converted, but
      those have now been dropped.
      The only thing left to do is actually delete all references to NET_MULTI
      and code that is compiled when that is not defined.  So here we scrub the
      core code.
      Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
    • Graeme Russ's avatar
      console: Implement pre-console buffer · 9558b48a
      Graeme Russ authored
      Allow redirection of console output prior to console initialisation to a
      temporary buffer.
      To enable this functionality, the board (or arch) must define:
       - CONFIG_PRE_CONSOLE_BUFFER - Enable pre-console buffer
       - CONFIG_PRE_CON_BUF_ADDR - Base address of pre-console buffer
       - CONFIG_PRE_CON_BUF_SZ - Size of pre-console buffer (in bytes)
      The pre-console buffer will buffer the last CONFIG_PRE_CON_BUF_SZ bytes
      Any earlier characters are silently dropped.
  8. 30 Sep, 2011 1 commit
    • Timur Tabi's avatar
      powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros · e46fedfe
      Timur Tabi authored
      macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS.
      This is necessary for the assembly-language code that relocates CCSR, since
      the assembler does not understand 64-bit constants.
      CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the
      should not be defined in a board header file.  Similarly,
      CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so
      it should also not be defined in the board header file.
      CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that
      and so CCSR will not be relocated.
      Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot
      builds (e.g. NAND) are required to relocate CCSR only during the last stage
      (i.e. the "real" U-Boot).  All other stages should define
      CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated.
      README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros.
      Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  9. 11 Sep, 2011 1 commit
  10. 03 Aug, 2011 1 commit
  11. 31 Jul, 2011 1 commit
  12. 29 Jul, 2011 1 commit
  13. 28 Jul, 2011 1 commit
  14. 26 Jul, 2011 3 commits
  15. 17 Jul, 2011 1 commit
  16. 16 Jul, 2011 2 commits
  17. 11 Jul, 2011 1 commit
  18. 04 Jul, 2011 2 commits
    • Aneesh V's avatar
      armv7: add PL310 support to u-boot · 93bc2193
      Aneesh V authored
      PL310 is the L2$ controller from ARM used in many SoCs
      including the Cortex-A9 based OMAP4430
      Add support for some of the key PL310 operations
      	- Invalidate all
      	- Invalidate range
      	- Flush(clean & invalidate) all
      	- Flush range
      Signed-off-by: default avatarAneesh V <aneesh@ti.com>
    • Aneesh V's avatar
      armv7: cache maintenance operations for armv7 · 2c451f78
      Aneesh V authored
      - Add a framework for layered cache maintenance
      	- separate out SOC specific outer cache maintenance from
      	  maintenance of caches known to CPU
      - Add generic ARMv7 cache maintenance operations that affect all
        caches known to ARMv7 CPUs. For instance in Cortex-A8 these
        opertions will affect both L1 and L2 caches. In Cortex-A9
        these will affect only L1 cache
      - D-cache operations supported:
      	- Invalidate entire D-cache
      	- Invalidate D-cache range
      	- Flush(clean & invalidate) entire D-cache
      	- Flush D-cache range
      - I-cache operations supported:
      	- Invalidate entire I-cache
      - Add maintenance functions for TLB, branch predictor array etc.
      - Enable -march=armv7-a so that armv7 assembly instructions can be
      Signed-off-by: default avatarAneesh V <aneesh@ti.com>
  19. 01 Jul, 2011 1 commit
    • Alex Waterman's avatar
      NAND: Add 16bit NAND support for the NDFC · eced4626
      Alex Waterman authored
      This patch adds support for 16 bit NAND devices attached to the
      NDFC on ppc4xx processors. Two config entries were added:
        CONFIG_SYS_NDFC_16        - Setting this tells the NDFC that a
      			      16 bit device is attached.
        CONFIG_SYS_NDFC_EBC0_CFG  - This is for the External Bus
      			      Controller configuration register.
      Also, a new ndfc_read_byte() function was added which does not
      first convert the data to little endian.
      The NAND SPL was also modified to do 16bit bad block testing
      when a 16 bit chip is being used.
      Signed-off-by: default avatarAlex Waterman <awaterman@dawning.com>
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
  20. 22 Jun, 2011 1 commit
  21. 20 May, 2011 1 commit
    • Kumar Gala's avatar
      powerpc/fsl_pci: Fix device tree fixups for newer platforms · 8f29084a
      Kumar Gala authored
      We assumed that only a small set of compatiable strings would be needed
      to find the PCIe device tree nodes to be fixed up.  However on newer
      platforms the simple rules no longer work.  We need to allow specifying
      the PCIe compatiable string for each individual SoC.
      We introduce CONFIG_SYS_FSL_PCIE_COMPAT for this purpose and set it if
      the default isn't sufficient.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
  22. 19 May, 2011 1 commit
  23. 12 May, 2011 3 commits
  24. 30 Apr, 2011 1 commit
    • Macpaul Lin's avatar
      cmd_ide: enhance new feature "CONFIG_IDE_AHB" · 0abddf82
      Macpaul Lin authored
      Although most IDE controller is designed to be connected to PCI bridge,
      there are still some IDE controller support AHB interface for SoC design.
      The driver implementation of these IDE-AHB controllers differ from other
      IDE-PCI controller, some additional registers and commands access is required
      during CMD/DATA I/O. Hence a configuration "CONFIG_IDE_AHB" in cmd_ide.c is
      required to be defined to support these kinds of SoC controllers. Such as
      Faraday's FTIDE020 series and Global Unichip's UINF-0301.
      Signed-off-by: default avatarMacpaul Lin <macpaul@andestech.com>
  25. 29 Apr, 2011 1 commit