1. 26 Oct, 2011 23 commits
  2. 25 Oct, 2011 6 commits
    • Anton staaf's avatar
      part_efi: dcache: allocate cacheline aligned buffers · f75dd584
      Anton staaf authored
      
      
      Currently part_efi.c allocates buffers for the gpt_header, the
      legacy_mbr, and the pte (partition table entry) that may be
      incorrectly aligned for DMA operations.
      
      This patch uses ALLOC_CACHE_ALIGN_BUFFER for the stack allocated
      buffers and memalign to replace the malloc of the pte.
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
      f75dd584
    • Anton staaf's avatar
      mmc: dcache: allocate cache aligned buffers for ext_csd · a1969923
      Anton staaf authored
      
      
      Currently the mmc_change_freq and mmc_startup functions allocates
      buffers on the stack that are passed down to the MMC device driver.
      These buffers could be unaligned to the L1 dcache line size.  This
      causes problems when using DMA and with caches enabled.
      
      This patch correctly cache alignes the buffers used for reading the
      ext_csd data from an MMC device.
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      a1969923
    • Anton staaf's avatar
      ext2: Cache line aligned partial sector bounce buffer · 4c1cd721
      Anton staaf authored
      
      
      Currently, if a device read request is done that does not begin or end
      on a sector boundary a stack allocated bounce buffer is used to perform
      the read, and then just the part of the sector that is needed is copied
      into the users buffer.  This stack allocation can mean that the bounce
      buffer will not be aligned to the dcache line size.  This is a problem
      when caches are enabled because unaligned cache invalidates are not
      safe.
      
      This patch uses ALLOC_CACHE_ALIGN_BUFFER to create a stack allocated
      cache line size aligned bounce buffer.
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Dave Liu <r63238@freescale.com>
      Cc: Andy Fleming <afleming@gmail.com>
      Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      
      Change-Id: I32e1594d90ef039137bb219b0f7ced55768744ff
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
      4c1cd721
    • Anton staaf's avatar
      mmc: dcache: allocate cache aligned buffer for scr and switch_status · f781dd38
      Anton staaf authored
      
      
      Currently the sd_change_freq function allocates two buffers on the
      stack that it passes down to the MMC device driver.  These buffers
      could be unaligned to the L1 dcache line size.  This causes problems
      when using DMA and with caches enabled.
      
      This patch correctly cache alignes the buffers used for reading the
      scr register and switch status values from an MMC device.
      
      Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
      f781dd38
    • Anton staaf's avatar
      tegra: define CONFIG_SYS_CACHELINE_SIZE for tegra · 96d21237
      Anton staaf authored
      
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Tom Warren <twarren.nvidia@gmail.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      
      Change-Id: I5c4bcfc0bfe59158ff249fe3be6640eec6d3cc76
      Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
      96d21237
    • Anton staaf's avatar
      cache: add ALLOC_CACHE_ALIGN_BUFFER macro · 46a6d51c
      Anton staaf authored
      
      
      This macro is used to allocate cache line size aligned stack
      buffers for use with DMA hardware.
      Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      Cc: Kyungmin Park <kyungmin.park@samsung.com>
      Cc: Mike Frysinger <vapier@gentoo.org>
      Cc: Aneesh V <aneesh@ti.com>
      Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
      Cc: Wolfgang Denk <wd@denx.de>
      46a6d51c
  3. 24 Oct, 2011 3 commits
  4. 23 Oct, 2011 8 commits