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  1. 01 Apr, 2009 1 commit
    • Kumar Gala's avatar
      85xx: Introduce determine_mp_bootpg() helper. · c840d26c
      Kumar Gala authored 
      

Match determine_mp_bootpg() that was added for 86xx.  We need this to
address a bug introduced in v2009.03 with 86xx MP booting.  We have to
make sure to reserve the region of memory used for the MP bootpg() so
other u-boot code doesn't use it.

Also added a comment about how cpu_reset() is dealing w/an errata on
early 85xx MP HW.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      c840d26c
  3. 30 Mar, 2009 3 commits
  5. 09 Mar, 2009 1 commit
  7. 18 Feb, 2009 1 commit
  9. 17 Feb, 2009 5 commits
  11. 23 Jan, 2009 3 commits
  13. 13 Jan, 2009 1 commit
  15. 20 Dec, 2008 7 commits
    • Trent Piepho's avatar
      mpc8[56]xx: Put localbus clock in sysinfo and gd · ada591d2
      Trent Piepho authored 
      

Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.

This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.

checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.
Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
Acked-by: default avatarJon Loeliger <jdl@freescale.com>
      ada591d2
    • Trent Piepho's avatar
      mpc8568: Double local bus clock divider · 446c381e
      Trent Piepho authored 
      

The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.

Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.
Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
Acked-by: default avatarJon Loeliger <jdl@freescale.com>
      446c381e
    • Dave Liu's avatar
      85xx: Fix the boot window issue · f51f07eb
      Dave Liu authored 
      

If one custom board is using the 8MB flash, it is set
as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000.
The current start.S code will be broken at switch_as.

It is because the TLB1[15] is set as 16MB page size,
EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000.

For the 8MB flash case, the EPN = 0xefxxxxxx,
RPN = 0xffxxxxxx. Assume the virt address of switch_as
is 0xef7ff18c, the real address of the instruction at
switch_as should be 0xff7ff18c. the 0xff7ff18c is out
of the range of the default 8MB boot LAW window
0xff800000 - 0xffffffff.

So when we switch to AS1 address space at switch_as,
the core can't fetch the instruction at switch_as any
more. It will cause broken issue.
Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
      f51f07eb
    • Haiying Wang's avatar
      Set IVPR to kenrel entry point in second core boot page · 181a3650
      Haiying Wang authored 
      

Assuming the OSes exception vectors start from the base of kernel address, and
the kernel physical starting address can be relocated to an non-zero address.
This patch enables the second core to have a valid IVPR for debugger before
kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.
Signed-off-by: default avatarHaiying Wang <Haiying.Wang@freescale.com>
      181a3650
    • Trent Piepho's avatar
      mpc8xxx: LCRR[CLKDIV] is sometimes five bits · a5d212a2
      Trent Piepho authored 
      

On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.
Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
Acked-by: default avatarJon Loeliger <jdl@freescale.com>
      a5d212a2
    • Trent Piepho's avatar
      mpc8[56]xx: Put localbus clock in device tree · 58ec4866
      Trent Piepho authored 
      

Export the localbus frequency in the device tree, the same way the CPU, TB,
CCB, and various other frequencies are exported in their respective device
tree nodes.

Some localbus devices need this information to be programed correctly, so
it makes sense to export it along with the other frequencies.

Unfortunately, when someone wrote the localbus dts bindings, they didn't
bother to define what the "compatible" property should be.  So it seems no
one was quite sure what to put in their dts files.

Based on current existing dts files in the kernel source, I've used
"fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all
of the 85xx devices, and are looked for by the Linux code.  The eLBC is
apparently not entirely backward compatible with the pq3 LBC and so eLBC
equipped platforms like 8572 won't use pq3-localbus.

For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems
and is also looked for by the Linux code.  On MPC8641, I've also used
"fsl,mpc8641-localbus" as it is also commonly used in dts files, some of
which don't use "fsl,elbc" or any other acceptable name to match on.
Signed-off-by: default avatarTrent Piepho <tpiepho@freescale.com>
Acked-by: default avatarKumar Gala <galak@kernel.crashing.org>
Acked-by: default avatarJon Loeliger <jdl@freescale.com>
      58ec4866
    • Kumar Gala's avatar
      85xx: Add support to populate addr map based on TLB settings · ecf5b98c
      Kumar Gala authored 
      
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      ecf5b98c
  17. 06 Dec, 2008 1 commit
  19. 04 Dec, 2008 4 commits
  21. 10 Nov, 2008 3 commits
  23. 24 Oct, 2008 3 commits
    • Dave Liu's avatar
      85xx: Fix the incorrect register used for DDR erratum1 · ae5f943b
      Dave Liu authored 
      

The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.

Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.

Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.

Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).

Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.
Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
      ae5f943b
    • Kumar Gala's avatar
      85xx: Add basic e500mc core support · 0f060c3b
      Kumar Gala authored 
      

Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      0f060c3b
    • Kumar Gala's avatar
      85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number · a38a5b6e
      Kumar Gala authored 
      

Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      a38a5b6e
  25. 21 Oct, 2008 1 commit
  27. 18 Oct, 2008 4 commits
  29. 17 Oct, 2008 1 commit
  31. 08 Oct, 2008 1 commit