1. 12 Feb, 2009 1 commit
  2. 18 Oct, 2008 1 commit
  3. 03 Sep, 2008 1 commit
  4. 13 Jul, 2008 1 commit
  5. 11 Jul, 2008 2 commits
  6. 03 Jun, 2008 1 commit
  7. 20 May, 2008 1 commit
    • Wolfgang Denk's avatar
      Big white-space cleanup. · 53677ef1
      Wolfgang Denk authored
      
      
      This commit gets rid of a huge amount of silly white-space issues.
      Especially, all sequences of SPACEs followed by TAB characters get
      removed (unless they appear in print statements).
      
      Also remove all embedded "vim:" and "vi:" statements which hide
      indentation problems.
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      53677ef1
  8. 05 Jan, 2008 1 commit
    • Stefan Roese's avatar
      ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup · 845c6c95
      Stefan Roese authored
      
      
      On Katmai the complete auto-calibration somehow doesn't seem to
      produce the best results, meaning optimal values for RQFD/RFFD.
      This was discovered by GDA using a high bandwidth scope,
      analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
      so now on Katmai "only" RFFD is auto-calibrated.
      
      This patch also adds RDCC calibration as mentioned on page 7 of
      the AMCC PowerPC440SP/SPe DDR2 application note:
      "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      845c6c95
  9. 27 Dec, 2007 1 commit
  10. 06 Dec, 2007 1 commit
    • Stefan Roese's avatar
      ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards · a27044b1
      Stefan Roese authored
      
      
      This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
      setting the FIXD bit in the SDR0_MFR register. Here a description of the
      symptoms:
      
      Problem Description
      ------------------------------
      If a DMA is performed between memory and PCI with the DMA 1 Controller
      using prefetch, and as a result uses a special purpose buffer selected by
      the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
      the first part of the transfer sequence is performed twice. The
      PPC440SPe PCI Controller requests more data than was needed such that in
      the case of enforce memory protection, a host CPU  exception can occur.
      No data is corrupted, because data transfer is stopped in the PCI
      Controller. Prefetch enable is specified by setting DMA Configuration
      Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.
      
      Behavior that may be observed in a running system
      ---------------------------------------------------------------------------
      
      1. DMA performance is decreased because of the double access on the PCI bus
      interface.
      2. If an illegal access to some address on the PCI bus is detected at the
      system level, a machine check or similar system error may occur.
      
      Workarounds Available
      ----------------------------------
      
      1. Do not program prefetch. Note that a prefetch command cannot be programmed
      without selecting a special purpose buffer.
      2. To avoid crossing a physical boundary of the PCI slave device, add 512
      bytes of address to the PCI address range.
      
      This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
      from AMCC and slighly changed.
      Signed-off-by: default avatarPravin M. Bathija <pbathija@amcc.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      a27044b1
  11. 05 Nov, 2007 1 commit
  12. 31 Oct, 2007 3 commits
    • Stefan Roese's avatar
      ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode · d4cb2d17
      Stefan Roese authored
      
      
      This patch adds support for dynamic configuration of PCIe ports for the
      AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
      boards Yucca & Katmai and the 405EX board Kilauea.
      
      This dynamic configuration is done via the "pcie_mode" environement
      variable. This variable can be set to "EP" or "RP" for endpoint or
      rootpoint mode. Multiple values can be joined via the ":" delimiter.
      Here an example:
      
      pcie_mode=RP:EP:EP
      
      This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
      as endpoint.
      
      Per default Yucca will be configured as:
      pcie_mode=RP:EP:EP
      
      Per default Katmai will be configured as:
      pcie_mode=RP:RP:REP
      
      Per default Kilauea will be configured as:
      pcie_mode=RP:RP
      Signed-off-by: default avatarTirumala R Marri <tmarri@amcc.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      d4cb2d17
    • Stefan Roese's avatar
      ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2) · 026f7110
      Stefan Roese authored
      
      
      This patch is the first patch of a series to make the 440SPe PCIe code
      usable on different 4xx PPC platforms. In preperation for the new 405EX
      which is also equipped with PCIe interfaces.
      
      (2) This patch renames the functions from 440spe_ to 4xx_ with a
          little additional cleanup
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      026f7110
    • Stefan Roese's avatar
      ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1) · c7c6da23
      Stefan Roese authored
      
      
      This patch is the first patch of a series to make the 440SPe PCIe code
      usable on different 4xx PPC platforms. In preperation for the new 405EX
      which is also equipped with PCIe interfaces.
      
      (1) This patch renames the files from 440spe_pcie to 4xx_pcie
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      c7c6da23
  13. 15 Sep, 2007 1 commit
  14. 07 Sep, 2007 2 commits
    • Grzegorz Bernacki's avatar
      [PPC440SPe] PCIe environment settings for Katmai and Yucca · 6efc1fc0
      Grzegorz Bernacki authored
      
      
      - 'pciconfighost' is set by default in order to be able to scan bridges
      behind the primary host/PCIe
      
      - 'pciscandelay' env variable is recognized to allow for user-controlled
      delay before the PCIe bus enumeration; some peripheral devices require a
      significant delay before they can be scanned (e.g. LSI8408E); without the
      delay they are not detected
      Signed-off-by: default avatarGrzegorz Bernacki <gjb@semihalf.com>
      6efc1fc0
    • Grzegorz Bernacki's avatar
      [PPC440SPe] Improve PCIe configuration space access · 7f191393
      Grzegorz Bernacki authored
      
      
      - correct configuration space mapping
      - correct bus numbering
      - better access to config space
      
      Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
      first device on the first bus. We now allow to configure up to 16 buses;
      also, scanning for devices behind the PCIe-PCIe bridge is supported, so
      peripheral devices farther in hierarchy can be identified.
      Signed-off-by: default avatarGrzegorz Bernacki <gjb@semihalf.com>
      7f191393
  15. 25 Jun, 2007 1 commit
  16. 24 Mar, 2007 1 commit
  17. 01 Mar, 2007 1 commit
  18. 20 Feb, 2007 1 commit