1. 04 Apr, 2013 1 commit
    • Dirk Behme's avatar
      spi: mxc_spi: Fix ECSPI reset handling · d36b39bf
      Dirk Behme authored
      
      
      Reviewing the ECSPI reset handling shows two issues:
      
      1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg
         (ECSPIx_CONGREG) the i.MX6 technical reference manual states:
      
         -- cut --
         ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block
         and resets the internal logic with the exception of the ECSPI_CONREG.
         -- cut --
      
         Note the exception mentioned: The CONREG itself isn't reset.
      
         Fix this by manually writing the reset value 0 to the whole register.
         This sets the EN bit to zero, too (i.e. includes the old
         ~MXC_CSPICTRL_EN).
      
      2. We want to reset the whole SPI block here. So it makes no sense
         to first read the old value of the CONREG and write it back, later.
         This will give us the old (historic/random) value of the CONREG back.
         And doesn't reset the CONREG.
      
         To get a clean CONREG after the reset of the block, too, don't use
         the old (historic/random) value of the CONREG while doing the reset.
         And read the clean CONREG after the reset.
      
      This was found while working on a SPI boot device where the i.MX6 boot
      ROM has already initialized the SPI block. The initialization by the
      boot ROM might be different to what the U-Boot driver wants to configure.
      I.e. we need a clean reset of SPI block, including the CONREG.
      
      Signed-off-by: default avatarDirk Behme <dirk.behme@de.bosch.com>
      CC: Stefano Babic <sbabic@denx.de>
      CC: Fabio Estevam <fabio.estevam@freescale.com>
      d36b39bf
  2. 03 Apr, 2013 14 commits
  3. 20 Mar, 2013 7 commits
  4. 15 Mar, 2013 4 commits
  5. 14 Mar, 2013 14 commits