1. 22 Sep, 2009 1 commit
  2. 11 Sep, 2009 1 commit
    • Stefan Roese's avatar
      ppc4xx: Big cleanup of PPC4xx defines · d1c3b275
      Stefan Roese authored
      
      
      This patch cleans up multiple issues of the 4xx register (mostly
      DCR, SDR, CPR, etc) definitions:
      
      - Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
      - Change the defines to better match the names from the
        user's manuals (e.g. cprpllc -> CPR0_PLLC)
      - Removal of some unused defines
      
      Please test this patch intensive on your PPC4xx platform. Even though
      I tried not to break anything and tested successfully on multiple
      4xx AMCC platforms, testing on custom platforms is recommended.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      d1c3b275
  3. 04 Sep, 2009 1 commit
  4. 26 Aug, 2009 9 commits
  5. 25 Aug, 2009 1 commit
    • Feng Kan's avatar
      ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driver · 68e74567
      Feng Kan authored
      
      
      Fix ECC Correction bug where the byte offset location were double
      flipped causing correction routine to toggle the wrong byte location
      in the ECC segment. The ndfc_calculate_ecc routine change the order
      of getting the ECC code.
              /* The NDFC uses Smart Media (SMC) bytes order */
              ecc_code[0] = p[2];
              ecc_code[1] = p[1];
              ecc_code[2] = p[3];
      But in the Correction algorithm when calculating the byte offset
      location, the s1 is used as the upper part of the address. Which
      again reverse the order making the final byte offset address
      location incorrect.
      	byteoffs = (s1 << 0) & 0x80;
      	.
      	.
      	byteoffs |= (s0 >> 4) & 0x08;
      The order is change to read it in straight and let the correction
      function to revert it to SMC order.
      Signed-off-by: default avatarFeng Kan <fkan@amcc.com>
      Acked-by: default avatarVictor Gallardo <vgallardo@amcc.com>
      Acked-by: default avatarProdyut Hazarika <phazarika@amcc.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      68e74567
  6. 21 Aug, 2009 2 commits
  7. 13 Aug, 2009 1 commit
  8. 09 Aug, 2009 1 commit
  9. 08 Aug, 2009 2 commits
  10. 07 Aug, 2009 1 commit
  11. 17 Jul, 2009 1 commit
    • Scott Wood's avatar
      Remove legacy NAND and disk on chip code. · be33b046
      Scott Wood authored
      
      
      Legacy NAND had been scheduled for removal.  Any boards that use this
      were already not building in the previous release due to an #error.
      
      The disk on chip code in common/cmd_doc.c relies on legacy NAND,
      and it has also been removed.  There is newer disk on chip code
      in drivers/mtd/nand; someone with access to hardware and sufficient
      time and motivation can try to get that working, but for now disk
      on chip is not supported.
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
      be33b046
  12. 16 Jul, 2009 5 commits
  13. 13 Jul, 2009 1 commit
    • Po-Yu Chuang's avatar
      issue write command to base for JEDEC flash · b4db4a76
      Po-Yu Chuang authored
      
      
      For JEDEC flash, we should issue word programming command relative to
      base address rather than sector base address. Original source makes
      SST Flash fails to program sectors which are not on the 0x10000 boundaries.
      
      e.g.
      SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector
      is 0x1000 bytes.
      
      Thus, if we issue command to "sector base (0x41000) + offset(0x5555)",
      it sends to 0x46555 and the chip fails to recognize that address.
      
      This patch is tested with SST39LF040.
      Signed-off-by: default avatarPo-Yu Chuang <ratbert@faraday-tech.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      b4db4a76
  14. 08 Jul, 2009 1 commit
  15. 07 Jul, 2009 8 commits
  16. 06 Jul, 2009 4 commits