- 22 Sep, 2009 1 commit
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Paul Gibson authored
Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
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- 11 Sep, 2009 1 commit
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Stefan Roese authored
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by:
Stefan Roese <sr@denx.de>
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- 04 Sep, 2009 1 commit
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Scott Wood authored
Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 26 Aug, 2009 6 commits
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Sandeep Paulraj authored
This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by:
Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Sandeep Paulraj authored
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by:
Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by:
Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Ilya Yanok authored
Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too. Signed-off-by:
Ilya Yanok <yanok@emcraft.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Sandeep Paulraj authored
This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by:
Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by:
Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Matthias Kaehlcke authored
Add KB9202 NAND driver Signed-off-by:
Matthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 25 Aug, 2009 1 commit
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Feng Kan authored
Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code. /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] = p[2]; ecc_code[1] = p[1]; ecc_code[2] = p[3]; But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect. byteoffs = (s1 << 0) & 0x80; . . byteoffs |= (s0 >> 4) & 0x08; The order is change to read it in straight and let the correction function to revert it to SMC order. Signed-off-by:
Feng Kan <fkan@amcc.com> Acked-by:
Victor Gallardo <vgallardo@amcc.com> Acked-by:
Prodyut Hazarika <phazarika@amcc.com> Signed-off-by:
Stefan Roese <sr@denx.de>
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- 21 Aug, 2009 1 commit
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Giulio Benetti authored
Signed-off-by: giulio.benetti@micronovasrl.com Acked-by:
Wolfgang Denk <wd@denx.de> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 08 Aug, 2009 2 commits
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Dirk Behme authored
Signed-off-by:
Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by:
Dirk Behme <dirk.behme@googlemail.com>
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Dirk Behme authored
Signed-off-by:
Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by:
Dirk Behme <dirk.behme@googlemail.com>
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- 07 Aug, 2009 1 commit
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Matthias Ludwig authored
Embedd chip select configuration into struct for gpmc config instead of having it completely separated as suggested by Wolfgang Denk on http://lists.denx.de/pipermail/u-boot/2009-May/052247.html Signed-off-by:
Matthias Ludwig <mludwig@ultratronik.de>
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- 17 Jul, 2009 1 commit
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Scott Wood authored
Legacy NAND had been scheduled for removal. Any boards that use this were already not building in the previous release due to an #error. The disk on chip code in common/cmd_doc.c relies on legacy NAND, and it has also been removed. There is newer disk on chip code in drivers/mtd/nand; someone with access to hardware and sufficient time and motivation can try to get that working, but for now disk on chip is not supported. Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 16 Jul, 2009 4 commits
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Stefan Roese authored
Now that the 4xx NAND driver ndfc is moved to the common NAND driver directory we don't need this #ifdef's anymore. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Valeriy Glushkov authored
Signed-off-by:
Valeriy Glushkov <gvv@lstec.com> Signed-off-by:
Paulraj, Sandeep <s-paulraj@ti.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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David Brownell authored
Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 08 Jul, 2009 1 commit
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Prafulla Wadaskar authored
This patch adds a NAND driver for the Marvell Kirkwood SoC's Signed-off-by:
Prafulla Wadaskar <prafulla@marvell.com> Acked-by:
Scott Wood <scottwood@freescale.com>
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- 07 Jul, 2009 7 commits
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Mingkai Hu authored
The bbt descriptors contains the pointer to the bbt pattern which are statically initialized memory struct. When relocated to RAM, these pointers will continue point to NOR flash(or L2 SRAM, or other boot device). If the contents of NOR flash changed or L2 SRAM disabled, it'll hang the system. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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The S3C2410 NAND driver source file is included in the makefile instead of the object file. Signed-off-by:
Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
nand_util currently uses size_t which is arch dependent and not always a unsigned long. Now use loff_t, as does the linux mtd layer. Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Mike Frysinger authored
The BF537-STAMP Blackfin board had a driver for working with NAND devices that are simply memory mapped. Since there is nothing Blackfin specific about this, generalize the driver a bit so that everyone can leverage it. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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David Brownell authored
Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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David Brownell authored
Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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David Brownell authored
Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by:
David Brownell <dbrownell@users.sourceforge.net> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- 06 Jul, 2009 1 commit
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Thomas Lange authored
NAND module should not modify EMIF registers unrelated to CS2 that is used for NAND, i.e. do not modify EWAIT config register or registers for other Chip Selects. Without this patch, EMIF configurations made in board_init() will be invalidated. Signed-off-by:
Thomas Lange <thomas@corelatus.se>
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- 12 Jun, 2009 3 commits
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Stefan Roese authored
This patch adds NAND Flash Controller driver for MPC5121 revision 2. All device features, except hardware ECC and power management, are supported. This NFC driver replaces the one orignally posted by John Rigby: "[PATCH] Freescale NFC NAND driver" It's a port of the Linux driver version posted by Piotr Ziecik a few weeks ago. Using this driver has the following advantages (from my point of view): - Compatibility with the Linux NAND driver (e.g. ECC usage) - Better code quality in general - Resulting U-Boot image is a bit smaller (approx. 3k) - Better to sync with newer Linux driver versions The only disadvantage I can see, is that HW-ECC is not supported right now. But this could be added later (e.g. port from Linux driver after it's supported there). Using HW-ECC on the MCP5121 NFC has a general problem because of the ECC usage in the spare area. This collides with JFFS2 for example. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Piotr Ziecik <kosmo@semihalf.com> Cc: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Scott Wood <scottwood@freescale.com>
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Stefan Roese authored
This new define enables mtdcore.c compilation and with this we can select the MTD device infrastructure needed for the reworked mtdparts command. We now have the 2 MTD infrastructure defines, CONFIG_MTD_DEVICE and CONFIG_MTD_PARTITIONS. CONFIG_MTD_DEVICE is needed (as explained above) for the "mtdparts" command and CONFIG_MTD_PARTITIONS is needed for UBI. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com>
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Stefan Roese authored
This patch brings the U-Boot MTD infrastructure in sync with the current Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size support and a resync of the mtdpart.c file which has seen multiple fixes meanwhile. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Kyungmin Park <kmpark@infradead.org>
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- 23 May, 2009 1 commit
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Stefan Roese authored
This patch enables Smart Media (SMC) ECC byte ordering which is used on the PPC4xx NAND FLASH controller (NDFC). Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Signed-off-by:
Stefan Roese <sr@denx.de> Acked-by:
Scott Wood <scottwood@freescale.com>
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- 27 Apr, 2009 2 commits
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Stefan Roese authored
With this patch the NAND and OneNAND devices are registered in the MTD subsystem and can then be referenced by the mtdcore code (e.g. get_mtd_device_nm()). This is needed for the new "ubi part" command syntax without the flash type parameter (nor|nand|onenand). Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
This patch removes this compilation warning when CONFIG_MTD_PARTITIONS is defined: nand_base.c: In function 'nand_release': nand_base.c:2922: warning: implicit declaration of function 'del_mtd_partitions' Signed-off-by:
Stefan Roese <sr@denx.de>
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- 06 Apr, 2009 1 commit
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Graf Yang authored
We need to make sure the data written to the nand flash controller makes it there before we start polling its status register. Otherwise, we may get stale data and return before the controller is actually ready. Signed-off-by:
Graf Yang <graf.yang@analog.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Acked-by:
Scott Wood <scottwood@freescale.com>
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- 30 Mar, 2009 2 commits
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 23 Mar, 2009 3 commits
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Wolfgang Grandegger authored
The NAND flash on the TQM8548_BE modules requires a short delay after running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE requires a further short delay after writing out a buffer. Normally the R/B pin should be checked, but it's not connected on the TQM8548_BE. The corresponding Linux FSL UPM driver uses similar delay points at the same locations. To manage these extra delays in a more general way, I introduced the "wait_flags" field allowing the board-specific driver to specify various types of extra delay. Signed-off-by:
Wolfgang Grandegger <wg@grandegger.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Wolfgang Grandegger authored
For the NAND chips on the TQM8548 modules, a special chip-select logic is used. It uses dedicated address lines to be set via UPM machine address register (mar). This patch adds such support to the FSL-UPM driver. Signed-off-by:
Wolfgang Grandegger <wg@grandegger.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Wolfgang Grandegger authored
This patch adds support for multi-chip NAND devices to the FSL-UPM driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now called with the argument "chip_nr" to allow testing the proper chip select line. The NAND support of the MPC8360ERDK is updated as well. No other boards are currently using the FSL UPM driver. Signed-off-by:
Wolfgang Grandegger <wg@grandegger.com> Signed-off-by:
Scott Wood <scottwood@freescale.com>
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