1. 05 Apr, 2017 8 commits
    • Ye Li's avatar
      MLK-14326-3 mx6qsabreauto: Enable OF_CONTROL and DM driver · d5f904fc
      Ye Li authored
      Enable OF_CONTROL and DM driver on mx6qsabreauto.
      1. Add the imx6qsabreauto relevant DTS file for using DTB.
      2. Modify PMIC initialization codes to use DM PMIC driver.
      3. Modify to use PCA953X DM driver
      4. Remove NAND from default, since the default imx6q-sabreauto.dts disabled
         the nand. The pins are conflicted with UART3, while UART3 is enabled.
      5. For NAND build configuration, remove the USB, since the imx6q-sabreauto-gpmi-weim.dts
         will have pin conflicts on steer logic.
      6. GPIO requests added.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-14363 mx6qsabreauto: Fix ethernet PHY setting issue · b9c64d0e
      Ye Li authored
      The PHY settings for RGMII has been removed from mx6qsabreauto board codes,
      due to the atheros PHY driver have updated to use same configuration for
      AR8031 and AR8035, while this configuration is duplicated as we set in board codes.
      But in recent codes, the PHY driver added a patch for AR8031 independent config.
      So needs to add the PHY settings back to the board codes.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Ye Li's avatar
      MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATA · 70bc3dd2
      Ye Li authored
      We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
      ref clock will impact the SATA ref 100Mhz clock.  If SATA is initialized before
      this changing, SATA read/write can't work after it. And we have to re-init SATA.
      The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
      This patch is an work around that moves the ENET clock setting
      (enable_fec_anatop_clock) from ethernet init to board_init which is prior
      than SATA initialization. So there is no PLL6 change after SATA init.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit fd8fbf7fa0b10199ac89cd13cae851149f51accb)
    • Ye.Li's avatar
      MLK-11230 imx6: USB: Modify OTG ID pin pad setting to pull up · f8f50ba4
      Ye.Li authored
      Set the ID pin pad to pull up not the pull down at default, otherwise
      we can't enter the device mode, but always detect as host.
      After this change we have to use portA cable to play as host,
      and use portB cable for device.
      Signed-off-by: default avatarYe.Li <B37916@freescale.com>
      (cherry picked from commit b315d6b36a913d75d25284320e69050ebdf7a7eb)
    • Ye Li's avatar
      MLK-12493-1 Add support for various boot device · b3b794bf
      Ye Li authored
      Add support for various boot devices like NAND, QSPINOR, SPINOR,
      Modify board level files to support the feature and add corresponding defconfig files
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 72c35e80b86f7f75a52db45959793882bb730793)
    • Ye Li's avatar
      MLK-12495 mx6: Add LDO bypass support · 8f8699a8
      Ye Li authored
      Port LDO bypass support from v2015 to support the features:
      1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
         enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
         on the flatten device tree file.
      2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
         on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
         reboot whole board, so split these code to independent function so that board file
         can call it freely.
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
      (cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
    • Peng Fan's avatar
      MLK-12436-8: imx: mx6qsabreauto: misc board update · 4798ccf6
      Peng Fan authored
      To Align with imx_v2016.03.
      1. Add USDHC1 support on mother board
      2. Add SPINOR flash support.
      3. Add enet ref clk pinmux setting and enet settings
      4. Use CONFIG_SYS_USE_EIMNOR to wrap eimnor settings.
      5. update mmc board settings
      6. update board_init and move nand settings to board_init, but not in
      7. update pmic settings to align with datasheet.
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      (cherry picked from commit f05f2281548ab7b47f69b2c517eb6f85ad09a5d2)
      Signed-off-by: default avatarYe Li <ye.li@nxp.com>
    • Peng Fan's avatar
      MLK-12434-3: mx6sabre: dynamic setting mmcdev and mmcroot · 7810c811
      Peng Fan authored
      Dynamic setting mmcdev and mmcroot for mx6sabresd and mx6qsabreauto.
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      (cherry picked from commit 14040e07549a394500c11e815f31299e4fb0ac50)
  2. 02 Jan, 2017 1 commit
    • Fabio Estevam's avatar
      mx6qsabreauto: Fix the EIM clock for the mx6qp variant · cfb37772
      Fabio Estevam authored
      On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the
      MX6DQP it is '3'.
      This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of
      132 MHz.
      Instead of relying on the POR values for the CSMR1 register, make sure to
      manually configure the clk_eim_slow_sel field as '00' so that EIM clock is
      derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM
      clock can be AXI clock divided by 2.
      This way a consistent EIM clock frequency is configured for all the mx6
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      Acked-by: default avatarPeng Fan <peng.fan@nxp.com>
  3. 23 Sep, 2016 1 commit
  4. 12 Jul, 2016 1 commit
  5. 31 May, 2016 1 commit
  6. 24 May, 2016 1 commit
  7. 03 Jan, 2016 1 commit
  8. 02 Sep, 2015 1 commit
    • Peng Fan's avatar
      imx: clock support enet2 anatop clock support · 6d97dc10
      Peng Fan authored
      To i.MX6SX/UL, two ethernet interfaces are supported.
      Add ENET2 clock support:
      1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
         To value 1, only i.MX6SX/UL can pass the check.
      2. Modify board code who use this api to follow new api prototype.
      Signed-off-by: default avatarPeng Fan <Peng.Fan@freescale.com>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
      Cc: Stefano Babic <sbabic@denx.de>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
  9. 02 Aug, 2015 2 commits
    • Peng Fan's avatar
      imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support · 361b715b
      Peng Fan authored
      1. Add DDR script for mx6qpsabreauto board.
      2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
         and init the enet pll output to 125Mhz.
      3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
      Build target: mx6qpsabreauto_config
      Boot Log:
      U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800)
      CPU:   Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz)
      CPU:   Automotive temperature grade (-40C to 125C) at 34C
      Reset cause: POR
      Board: MX6Q-Sabreauto revA
      I2C:   ready
      DRAM:  2 GiB
      PMIC:  PFUZE100 ID=0x10
      Flash: 32 MiB
      NAND:  0 MiB
      MMC:   FSL_SDHC: 0
      *** Warning - bad CRC, using default environment
      No panel detected: default to HDMI
      Display: HDMI (1024x768)
      In:    serial
      Out:   serial
      Err:   serial
      Net:   FEC [PRIME]
      Hit any key to stop autoboot:  0
      In this patch, we still add a new config mx6qpsabreauto_config,
      since SPL is not supported now, and IMX_CONFIG is needed at
      build time, so add this config. Future, when SPL is converted,
      this config can be removed.
      Signed-off-by: default avatarPeng Fan <Peng.Fan@freescale.com>
      Signed-off-by: default avatarRobin Gong <b38343@freescale.com>
      Signed-off-by: default avatarYe.Li <B37916@freescale.com>
      Reviewed-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
    • Peng Fan's avatar
      imx: mx6sabresd/sabreauto runtime setting fdt_file · e6fc8995
      Peng Fan authored
      Detect the SOC and board variant at runtime and change the dtb name,
      but not hardcoding the fdt_file env variable.
      Take the following patch as a reference.
      "mx6cuboxi: Load the correct 'fdtfile' variable"
      Signed-off-by: default avatarPeng Fan <Peng.Fan@freescale.com>
      Reviewed-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Acked-by: default avatarStefano Babic <sbabic@denx.de>
  10. 11 Feb, 2015 1 commit
  11. 10 Feb, 2015 1 commit
  12. 20 Nov, 2014 2 commits
  13. 13 Nov, 2014 1 commit
  14. 03 Nov, 2014 1 commit
    • Ye.Li's avatar
      imx: mx6 sabreauto: Add board support for USB EHCI · 8fe280f3
      Ye.Li authored
      On mx6 sabreauto board, there are two USB ports:
      0: OTG
      1: HOST
      The EHCI driver is enabled for this board, but the IOMUX and VBUS power
      control is not implemented, which cause both USB port failed to work.
      This patch fix the problem by adding the board support codes.
      Since the power control uses the GPIO pin from port expander MAX7310,
      the PCA953X driver is enabled for accessing the MAX7310.
      The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
      its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
      handle GPR register setting.
      Signed-off-by: default avatarYe.Li <B37916@freescale.com>
  15. 21 Oct, 2014 2 commits
  16. 24 Sep, 2014 1 commit
    • Nikita Kiryanov's avatar
      spi: mxc: fix sf probe when using mxc_spi · 155fa9af
      Nikita Kiryanov authored
      MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
      across multiple transactions. This is set up by embedding the GPIO information
      in the CS value:
      cs = (cs | gpio << 8)
      This merge of cs and gpio data into one value breaks the sf probe command:
      if the use of gpio is required, invoking "sf probe <cs>" will not work, because
      the CS argument doesn't have the GPIO information in it. Instead, the user must
      use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
      cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
      type "sf probe 15872".
      This is inconsistent with the description of the sf probe command, and forces
      the user to be aware of implementaiton details.
      Fix this by introducing a new board function: board_spi_cs_gpio(), which will
      accept a naked CS value, and provide the driver with the relevant GPIO, if one
      is necessary.
      Cc: Eric Nelson <eric.nelson@boundarydevices.com>
      Cc: Eric Benard <eric@eukrea.com>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Tim Harvey <tharvey@gateworks.com>
      Cc: Stefano Babic <sbabic@denx.de>
      Cc: Tom Rini <trini@ti.com>
      Cc: Marek Vasut <marex@denx.de>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
      Reviewed-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>
  17. 16 Sep, 2014 1 commit
  18. 13 Jan, 2014 1 commit
  19. 17 Dec, 2013 1 commit
    • Eric Nelson's avatar
      i.MX6 (DQ/DLS): use macros for mux and pad declarations · b47abc36
      Eric Nelson authored
      This allows the use of either or both declarations from
      the files mx6q_pins.h and mx6dl_pins.h.
      All board files should include <asm/arch/mx6-pins.h>
      with one of the following defined in boards.cfg
          MX6Q   - for boards targeting i.MX6Q or i.MX6D
          MX6DL  - for boards targeting i.MX6DL
          MX6S   - for boards targeting i.MX6S
          MX6QDL - for boards that support any of the above with
                   run-time detection
      Pad declarations will be MX6_PAD_x for single-variant boards
      and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both
      processor classes.
      Signed-off-by: default avatarEric Nelson <eric.nelson@boundarydevices.com>
      Acked-by: default avatarStefano Babic <sbabic@denx.de>
  20. 13 Nov, 2013 1 commit
  21. 20 Sep, 2013 1 commit
  22. 24 Jul, 2013 1 commit
  23. 03 Jun, 2013 2 commits
  24. 28 Apr, 2013 2 commits
    • Benoît Thébaudeau's avatar
      imx: iomux-v3: Include PKE and PUE to pad control pull definitions · 7e2173cf
      Benoît Thébaudeau authored
      PUE requires PKE to mean something, as do pull values with PUE, so do not
      compell users to explicitly use PKE and PUE everywhere. This is also what is
      done on Linux and what has already been done for i.MX51.
      By the way, remove some unused pad control definitions.
      There is no change of behavior.
      Note that SPI_PAD_CTRL was defined by several boards with a pull value, but
      without PKE or PUE, which means that no pull was actually enabled in the pad.
      This might be a bug in those boards, but this patch does not change the
      behavior, so it just removes the meaningless pull value from those definitions.
      Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
    • Benoît Thébaudeau's avatar
      imx: Homogenize and fix fuse register definitions · 8f3ff11c
      Benoît Thébaudeau authored
       - Homogenize prg_p naming (the reference manuals are not always self-consistent
         for that).
       - Add missing SCSx and bank registers.
       - Fix the number of banks on i.MX53.
       - Rename iim to ocotp in order to avoid confusion.
       - Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
         reference manual.
       - Merge the existing spinoff gp1 fuse definition on i.MX6.
       - Fix the number of banks on i.MX6.
      Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
      Acked-by: default avatarStefano Babic <sbabic@denx.de>
  25. 03 Apr, 2013 1 commit
  26. 07 Mar, 2013 1 commit
  27. 16 Oct, 2012 2 commits