1. 24 Sep, 2015 21 commits
  2. 23 Sep, 2015 1 commit
  3. 19 Sep, 2015 1 commit
    • Masahiro Yamada's avatar
      pinctrl: move dm_scan_fdt_node() out of pinctrl uclass · 8a5f6129
      Masahiro Yamada authored
      Commit c5acf4a2 ("pinctrl: Add the concept of peripheral IDs")
      added some additional change that was not mentioned in the git-log.
      
      That commit added dm_scan_fdt_node() in the pinctrl uclass binding.
      It should be handled by the simple-bus driver or the low-level
      driver, not by the pinctrl framework.
      
      I guess Simon's motivation was to bind GPIO banks located under the
      Rockchip pinctrl device.  It is true some chips have sub-devices
      under their pinctrl devices, but it is basically SoC-specific matter.
      
      This commit partly reverts commit c5acf4a2
      
       to keep the only
      pinctrl-generic features in the uclass.  The dm_scan_fdt_node()
      should be called from the rk3288_pinctrl driver.
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Acked-by: default avatarSimon Glass <sjg@chromium.org>
      Tested-by: default avatarSimon Glass <sjg@chromium.org>
      8a5f6129
  4. 17 Sep, 2015 16 commits
  5. 16 Sep, 2015 1 commit
    • Thierry Reding's avatar
      ARM: tegra114: Clear IDDQ when enabling PLLC · 8e1601d9
      Thierry Reding authored
      
      
      Enabling a PLL while IDDQ is high. The Linux kernel checks for this
      condition and warns about it verbosely, so while this seems to work
      fine, fix it up according to the programming guidelines provided in
      the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup
      Sequence"). The Tegra114 TRM doesn't contain this information, but
      the programming of PLLC is the same on Tegra114 and Tegra124.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
      8e1601d9