1. 20 Feb, 2016 2 commits
    • Alexey Brodkin's avatar
      arc: cache - utilize IO coherency (AKA IOC) engine · db6ce231
      Alexey Brodkin authored
      With release of ARC HS38 v2.1 new IO coherency engine could be built-in
      ARC core. This hardware module ensures coherency between DMA-ed data
      from peripherals and L2 cache.
      
      With L2 and IOC enabled there's no overhead for L2 cache manual
      maintenance which results in significantly improved IO bandwidth.
      Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
      db6ce231
    • Alexey Brodkin's avatar
      arc: cache - accommodate different L1 cache line lengths · 379b3280
      Alexey Brodkin authored
      ARC core could be configured with different L1 and L2 (AKA SLC) cache
      line lengths. At least these values are possible and were really used:
      32, 64 or 128 bytes.
      
      Current implementation requires cache line to be selected upon U-Boot
      configuration and then it will only work on matching hardware. Indeed
      this is quite efficient because cache line length gets hardcoded during
      code compilation. But OTOH it makes binary less portable.
      
      With this commit we allow U-Boot to determine real L1 cache line length
      early in runtime and use this value later on. This extends portability
      of U-Boot binary a lot.
      Signed-off-by: default avatarAlexey Brodkin <abrodkin@synopsys.com>
      379b3280
  2. 19 Feb, 2016 2 commits
  3. 18 Feb, 2016 4 commits
  4. 17 Feb, 2016 1 commit
  5. 16 Feb, 2016 23 commits
  6. 15 Feb, 2016 8 commits