1. 24 Jul, 2010 4 commits
  2. 23 Jul, 2010 9 commits
    • Stefan Roese's avatar
      ppc4xx: Enable "ecctest" command on t3corp · 1ffcb86c
      Stefan Roese authored
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      1ffcb86c
    • Stefan Roese's avatar
      ppc4xx: Enable "ecctest" command on katmai · e3722860
      Stefan Roese authored
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      e3722860
    • Stefan Roese's avatar
    • Stefan Roese's avatar
      ppc4xx: Add "ecctest" command to test/simulate ECC errors · 58eb869f
      Stefan Roese authored
      This patch adds the "ecctest" command to test and simulate ECC errors
      (single bit and/or double bit) while running from SDRAM. Currently only
      the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT).
      
      This is done by copying and calling functions, modifying the SDRAM
      controller operation mode, in internal SRAM/OCM.
      
      For correctable ECC errors (single bit) only the status will be printed
      since the DDR2 controller doesn't provide the faulting address:
      
      => ecctest 1000000 1
      Using address 01000000 for 1 bit ECC error injection
      ECC: Correctable error
      
      Uncorrectable ECC errors (double bit) will also display the faulting
      address:
      
      => ecctest 1000000 2
      Using address 01000000 for 2 bit ECC error injection
      ECC: Uncorrectable error at 0x0001000000
      
      To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST
      in the board config header.
      
      Tested on katmai and t3corp.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      58eb869f
    • Stefan Roese's avatar
      ppc4xx: DDR/ECC: Use correct macros to clear error status · b995d7cb
      Stefan Roese authored
      Use the correct macro instead of the hardcoded 0x4c to clear the ECC
      status in the 440/460 DDR(2) error status register after ECC
      initialization.
      
      Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
      (440GX) use a different registers to clear this error status. Use the
      correct ones.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      b995d7cb
    • Stefan Roese's avatar
      ppc4xx: Only define DDR2 registers for the correct PowerPC variants · 897d6abc
      Stefan Roese authored
      Make sure that some SDRAM/DDR2 registers are only defined for the PPC
      variants really implementing those registers.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      897d6abc
    • Stefan Roese's avatar
      ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values · eab98001
      Stefan Roese authored
      Using this define, a board can define an opimized RFDC value and use
      the auto calibration code to "tune" the remaining DDR2 controller
      calibration register.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      eab98001
    • Stefan Roese's avatar
      ppc4xx: T3CORP fixes and updates · 5bf39a96
      Stefan Roese authored
      This patch fixes some problems for the T3CORP board. Here the list
      of the changes:
      
      - Add 600-67 and 677 CPU frequency setting to chip_config
        command
      - Define CONFIG_DDR_RFDC_FIXED on t3corp:
        While using the "normal" auto calibration code, sometimes values for
        RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang
        upon relocation, while running from SDRAM). With this optimized RFDC
        value we can force this register and use the auto-calibration code to
        setup the remaining calibration registers.
      - Increase sizes of FPGA chips selects
      - EBC timing updated OEN=3 for 66 MHz EBC speed
      - Change ext. IRQ2 setup to level-low active
      - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL
      
      By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the
      chip busy status. This is now used instead of the data toggle method which
      is used historically by default in the common CFI driver. With this change
      a problem with not written data is solved on this board, where a 32 byte
      block of data is still erased instead of filled with the correct content
      after these commands:
      
      => erase 0xfc100000 +0x1000000
      
      ....................................................................
      done
      Erased 128 sectors
      => cp.b 0x100000 0xfc100000 0x1000000
      Copy to Flash... done
      => cmp.b 0x100000 0xfc100000 0x1000000
      byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff)
      Total of 12637888 bytes were the same
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      5bf39a96
    • Rupjyoti Sarmah's avatar
      ppc4xx/Canyonlands added USB board callbacks · 17a68444
      Rupjyoti Sarmah authored
      Functions added to support board callbacks for USB init. This
      isolates USB manipulations such that it is only touched if USB is
      used by U-Boot.
      Signed-off-by: default avatarDave Mitchell <dmitchell@appliedmicro.com>
      Signed-off-by: default avatarRupjyoti Sarmah <rsarmah@appliedmicro.com>
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      17a68444
  3. 22 Jul, 2010 1 commit
  4. 21 Jul, 2010 3 commits
  5. 20 Jul, 2010 11 commits
  6. 17 Jul, 2010 3 commits
  7. 16 Jul, 2010 9 commits