1. 02 Nov, 2017 7 commits
  2. 12 May, 2017 1 commit
  3. 25 Apr, 2017 1 commit
  4. 05 Apr, 2017 5 commits
  5. 08 Feb, 2017 1 commit
    • Simon Glass's avatar
      dm: core: Replace of_offset with accessor · e160f7d4
      Simon Glass authored
      
      
      At present devices use a simple integer offset to record the device tree
      node associated with the device. In preparation for supporting a live
      device tree, which uses a node pointer instead, refactor existing code to
      access this field through an inline function.
      Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
      e160f7d4
  6. 07 Feb, 2017 1 commit
  7. 16 Dec, 2016 4 commits
  8. 31 Oct, 2016 1 commit
  9. 23 Sep, 2016 1 commit
  10. 12 Jul, 2016 1 commit
  11. 24 May, 2016 1 commit
  12. 03 Jan, 2016 2 commits
  13. 11 Sep, 2015 1 commit
  14. 02 Sep, 2015 1 commit
  15. 10 Jul, 2015 1 commit
  16. 18 Apr, 2015 2 commits
  17. 25 Oct, 2014 1 commit
  18. 09 Sep, 2014 2 commits
    • Fabio Estevam's avatar
      net: fec_mxc: Poll FEC_TBD_READY after polling TDAR · f599288d
      Fabio Estevam authored
      
      
      When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
      always cleared prior then the READY bit is cleared in the last BD, which causes
      FEC packets reception to always fail.
      
      As explained by Ye Li:
      
      "The TDAR bit is cleared when the descriptors are all out from TX ring, but on
      mx6solox we noticed that the READY bit is still not cleared right after TDAR.
      These are two distinct signals, and in IC simulation, we found that TDAR always
      gets cleared prior than the READY bit of last BD becomes cleared.
      In mx6solox, we use a later version of FEC IP. It looks like that this
      intrinsic behaviour of TDAR bit has changed in this newer FEC version."
      
      Fix this by polling the READY bit of BD after the TDAR polling, which covers the
      mx6solox case and does not harm the other SoCs.
      
      No performance drop has been noticed with this patch applied when testing TFTP
      transfers on several boards of different i.mx SoCs.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Acked-by: default avatarMarek Vasut <marex@denx.de>
      f599288d
    • Fabio Estevam's avatar
      net: fec_mxc: Adjust RX DMA alignment for mx6solox · db5b7f56
      Fabio Estevam authored
      
      
      mx6solox has a requirement for 64 bytes alignment for RX DMA transfer.
      Other SoCs work with the standard 32 bytes alignment.
      
      Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers,
      which addresses the needs from mx6solox and also works for the other SoCs.
      Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
      Acked-by: default avatarMarek Vasut <marex@denx.de>
      db5b7f56
  19. 11 Feb, 2014 1 commit
  20. 21 Nov, 2013 1 commit
    • Marek Vasut's avatar
      Net: FEC: Fix huge memory leak · 79e5f27b
      Marek Vasut authored
      
      
      The fec_halt() never free'd both RX and TX DMA descriptors that
      were allocated in fec_init(), nor did it free the RX buffers.
      Rework the FEC driver so that these descriptors and buffers are
      allocated only once in fec_probe().
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Fabio Estevam <fabio.estevam@freescale.com>
      Cc: Stefano Babic <sbabic@denx.de>
      79e5f27b
  21. 20 Sep, 2013 2 commits
  22. 21 Aug, 2013 1 commit
  23. 24 Jul, 2013 1 commit