1. 20 Apr, 2015 4 commits
    • Ying Zhang's avatar
      board/t208xrdb: VID support · e5abb92c
      Ying Zhang authored
      The fuse status register provides the values from on-chip
      voltage ID efuses programmed at the factory.
      These values define the voltage requirements for
      the chip. u-boot reads FUSESR and translates the values
      into the appropriate commands to set the voltage output
      value of an external voltage regulator.
      Signed-off-by: default avatarYing Zhang <b40530@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
    • Shengzhou Liu's avatar
      powerpc/t2080: enable erratum_a007186 for t2080 rev1.1 · 9ca0d35f
      Shengzhou Liu authored
      T2080 rev1.1 also needs erratum a007186.
      Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
    • Alexander Graf's avatar
      qemu-ppce500: Add support for 64bit CCSR map · e834975b
      Alexander Graf authored
      QEMU 2.3 changes the address layout of the CCSR map in the PV ppce500 machine
      to reside in higher address space.
      Unfortunately, this exposed a glitch in u-boot for ppce500: While providing
      a function to dynamically evaluate the CCSR region's position in physical
      address space, we never used it. Plus we forgot to support 64bit physical
      This patch fixes that mishap, making u-boot work fine with latest QEMU again.
      Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
      Reviewed-by: default avatarScott Wood <scottwood@freescale.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
    • Curt Brune's avatar
      MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register · d7c865bd
      Curt Brune authored
      According to the MPC8555/MPC8541 reference manual the SS_EN (source
      synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
      during initialization.
      >From section of that manual:
         Source synchronous enable. This bit field must be set during
         initialization. See Section 9.6.1, "DDR SDRAM Initialization
         Sequence," details.
         0 - Reserved
         1 - The address and command are sent to the DDR SDRAMs source
      In addition, Freescale application note AN2805 is also very clear that
      this bit must be set.
      This patch reverts a change introduced by commit
      Testing Done:
      Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
      and inspected the generated assembly code to verify the SS_EN bit was being
      set.  There is one extra instruction emitted:
        fff9b774: 65 29 80 00  oris    r9,r9,32768
      Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
      additional instructions were emitted related to this patch.
      Booted an image on a MPC8541 based board successfully.
      Signed-off-by: default avatarCurt Brune <curt@cumulusnetworks.com>
      Reviewed-by: default avatarYork Sun <yorksun@freescale.com>
  2. 18 Apr, 2015 36 commits