1. 24 Nov, 2014 1 commit
  2. 13 Nov, 2014 11 commits
  3. 12 Nov, 2014 2 commits
    • Thierry Reding's avatar
      ARM: cache-cp15: Use more accurate types · 25026fa9
      Thierry Reding authored
      
      
      size_t is the canonical type to represent variables that contain a size.
      Use it instead of signed integer. Physical addresses can be larger than
      32-bit, so use a more appropriate type for them as well. phys_addr_t is
      a type that is 32-bit on systems that use 32-bit addresses and 64-bit if
      the system is 64-bit or uses a form of physical address extension to use
      a larger address space on 32-bit systems. Using these types the same API
      can be implemented on a wider range of systems.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      25026fa9
    • Thierry Reding's avatar
      ARM: cache_v7: Various minor cleanups · b9297c22
      Thierry Reding authored
      
      
      Remove two gratuituous blank lines, uses u32 (instead of int) as the
      type for values that will be written to a register, moves the beginning
      of the variable declaration section to a separate line (rather than the
      one with the opening brace) and keeps the function signature on a single
      line where possible.
      Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
      Acked-by: default avatarSimon Glass <sjg@chromium.org>
      b9297c22
  4. 11 Nov, 2014 11 commits
  5. 10 Nov, 2014 1 commit
  6. 07 Nov, 2014 4 commits
    • Wolfgang Denk's avatar
      cppcheck cleanup: fix nullPointer errors · 0060517a
      Wolfgang Denk authored
      
      
      There are a number of places where U-Boot intentionally and legally
      accesses physical address 0x0000, for example when installing
      exception vectors on systems where these are located in low memory.
      
      Add "cppcheck-suppress nullPointer" comments to silence cppcheck
      where this is intentional and legal.
      Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
      0060517a
    • Stefan Roese's avatar
      arm: socfpga: Add socfpga_spim_enable() to reset_manager.c · a877bec3
      Stefan Roese authored
      
      
      This function will be needed by the upcoming Designware master SPI
      driver. As the SPI master controller is held in reset by the current
      Preloader implementation. So we need to release the reset for the
      driver to communicate with the controller.
      
      This function is called from arch_early_init_r() if the SPI
      driver is enabled.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      a877bec3
    • Stefan Roese's avatar
      arm: socfpga: Add DW master SPI clock to clock_manager.c · d2bb937d
      Stefan Roese authored
      
      
      This function will be needed by the upcoming Designware master SPI
      driver.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Pavel Machek <pavel@denx.de>
      d2bb937d
    • Stefan Roese's avatar
      arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates target · 51c580c6
      Stefan Roese authored
      
      
      This patch includes the latest DT sources for socfpga from the current
      Linux kernel. And enables CONFIG_OF_CONTROL for the new build target
      "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT
      support.
      
      Until this patch, the only SoCFPGA U-Boot target in mainline is
      "socfpga_cyclone5". This build target is not (yet) changed to support
      DT. So nothing changes for this target. Even though the long-term
      goal should be to move all SoCFPGA targets over to DT.
      
      One of the reasons to enable DT support in SoCFPGA is, that I need to
      support multiple different SPI controllers for this platform. This is
      the QSPI Cadence controller and the Designware SPI master controller.
      Both are implemented in the SoCFPGA. And enabling both controllers is
      only possible by using the new driver model (DM). The DM SPI code
      only supports DT based probing. So it was easier to move SoCFPGA to
      DT than to add the (deprecated) platform-data based probing to the
      DM SPI suport.
      
      Note that the image with the dtb embedded is u-boot-dtb.img. This needs
      to be used now for those DT enabled boards instead of u-boot.img.
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Marek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@altera.com>
      Cc: Vince Bridgers <vbridger@altera.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Pavel Machek <pavel@denx.de>
      Cc: Simon Glass <sjg@chromium.org>
      51c580c6
  7. 06 Nov, 2014 2 commits
  8. 05 Nov, 2014 8 commits