1. 17 Dec, 2013 5 commits
    • Nikita Kiryanov's avatar
      mtd: nand: omap: fix sw->hw->sw ecc switch · eb237a15
      Nikita Kiryanov authored
      When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values
      into the current nand chip's ecc.layout struct. This is done under the
      assumption that the struct exists only to store values, so it is OK to overwrite
      it, but there is at least one situation where this assumption is incorrect:
      When switching to 1 bit hamming code sw ecc, the job of assigning layout data
      is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a
      pointer to an existing struct prefilled with the appropriate values. This struct
      doubles as both data and layout definition, and therefore shouldn't be
      overwritten, but on the next switch to hardware ecc, this is exactly what's
      going to happen. The next time the user switches to software ecc, they're
      going to get a messed up ecc layout.
      Prevent this and possible similar bugs by explicitly using the
      private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode.
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Pekon Gupta <pekon@ti.com>
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
    • Tom Rini's avatar
      nand_util.c: Use '%zd' for length in nand_unlock debug print · 3ef1eadb
      Tom Rini authored
      length is size_t so needs to be '%zd' not '%d' to avoid warnings.
      Cc: Scott Wood <scottwood@freescale.com>
      Signed-off-by: default avatarTom Rini <trini@ti.com>
    • Nikita Kiryanov's avatar
      mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.size · 2528460c
      Nikita Kiryanov authored
      Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic
      platform" (d016dc42
      ) changed the way
      software ECC is configured, both during boot, and during ecc switch, in a way
      that is not backwards compatible with older systems:
      Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring
      for software ecc, relying on nand_scan_tail() to select a default for ecc.size
      (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize,
      which is likely to not be 256.
      Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert
      to the original behavior.
      Cc: Igor Grinberg <grinberg@compulab.co.il>
      Cc: Tom Rini <trini@ti.com>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Pekon Gupta <pekon@ti.com>
      Signed-off-by: default avatarNikita Kiryanov <nikita@compulab.co.il>
      Acked-by: default avatarPekon Gupta <pekon@ti.com>
    • Stefan Roese's avatar
      mtd: nand: omap_gpmc: cosmetic: Fix indentation · 5d7a49b9
      Stefan Roese authored
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Cc: Pekon Gupta <pekon@ti.com>
      Cc: Scott Wood <scottwood@freescale.com>
      [scottwood@freescale.com: wrap some long lines]
      Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
    • pekon gupta's avatar
      mtd: nand: omap: fix ecc-layout for HAM1 ecc-scheme · 69cc97f8
      pekon gupta authored
      As per OMAP3530 TRM referenced below [1]
      For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
       - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
       - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device
      Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
       *for x8 NAND Device*
       | xxxx   | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
       *for x16 NAND Device*
       | xxxxx  | xxxxx  | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] |
      This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
      For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.
      [1] OMAP3530: http://www.ti.com/product/omap3530
          TRM: http://www.ti.com/litv/pdf/spruf98x
      		Chapter-25: Initialization Sub-topic: Memory Booting
      		Section: NAND
      		Figure 25-19. ECC Locations in NAND Spare Areas
      Reported-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarPekon Gupta <pekon@ti.com>
      Tested-by: default avatarStefan Roese <sr@denx.de>
  2. 16 Dec, 2013 16 commits
  3. 13 Dec, 2013 19 commits